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//some example
. R8 t4 o c k' F% d0 a1 A' J, J# g3 d- y5 G' O" r) v6 Y! G# R% l
// define variable
7 I2 b$ l2 j: T& z1 bVARIABLE RVM1 0.077 // Metal-1 resistor
) V: U" W+ t. n: k) ]6 F. L+ JVARIABLE RVM2 0.055 // Metal-2 resistor j% f% t% C1 u3 q
VARIABLE RVM3 0.055 // Metal-3 resistor
+ S9 @: c* ~9 s$ ^4 G" T: K- H8 r0 h# O! {2 _. f% S' j K
// lvs option: `/ M2 Y x1 V. k2 h7 L+ M
LVS SPICE PREFER PINS YES2 T- `0 A! M4 C, U
LVS ABORT ON SUPPLY ERROR NO6 Z9 F4 S# {& }0 ?
LVS ALL CAPACITOR PINS SWAPPABLE YES0 d( Y+ }- k# k) b' A: ? @
LVS RECOGNIZE GATES NONE+ O9 n$ Y. l" _5 A
LVS IGNORE PORTS NO
: Z5 [- m+ \+ c/ N3 |LVS CHECK PORT NAMES YES" F/ P1 l9 M* d9 t; V
LVS REDUCE PARALLEL BIPOLAR YES
6 {8 A- O% H/ [2 o0 `1 E& _LVS REDUCE PARALLEL MOS YES, p5 V) H' ~ {2 j3 N" F& {
LVS REDUCE PARALLEL DIODES YES
: [+ E, t( |" `LVS REDUCE PARALLEL CAPACITORS YES$ O0 T# u5 v3 Z$ S+ O U, y, m3 @& \
LVS REDUCE PARALLEL RESISTORS YES
+ g2 p0 y6 }: D. K! yLVS REDUCE SERIES RESISTORS YES //Smashes series resistors# x; P, i; A5 h/ `' w
LVS REDUCE SERIES CAPACITORS YES //Smashes series capacitors
: ~- s4 ?: @" E$ YLVS REDUCE SPLIT GATES NO //Smashes MOS split-gates.
1 w% X& I1 T1 S. R0 M; U1 m//LVS FILTER UNUSED OPTION B D E O
& L& c4 M% f2 I7 K, @; G qLVS FILTER UNUSED OPTION AB RC RE RG8 T, q( H9 `" a6 F% x
LVS PROPERTY RESOLUTION MAXIMUM 65536 // ALL4 c! e: t8 u" ?, U! i
& Y( u* o' L% u5 ]" v! R) O+ u# h: `// layer definition
2 g/ D& B- A7 {# S2 N+ yLAYER DNW 1 // DNW -- Deep N-Well
$ ?" p- I- S: }: `6 N8 p: mLAYER NTN 11 // Native Device Blocked Implant
. b8 k" v! L) i% N3 wLAYER NWELL 3 // NW -- N-Well& S1 ~( @( Z+ L2 j0 T1 [' }% O
LAYER OD 8 6 7 // OD -- Thin Oxide! L3 N, P+ r" P7 U( l, _
: ^3 i g1 `5 x// layer operation3 n) ?6 b9 N5 d
rpolywo1 = POLYG AND RHDMY ! g7 ~9 T% b+ o1 h5 C& a. H( l" z
rpolywo2 = rpolywo1 AND RPO , N# g. A# z" L* l
diff = OD NOT RODMY
& D U/ `6 |& P. q' Rrp1 = RPDMY NOT INTERACT diff * p6 p, B; ^/ ]( |2 [
p1rdum = rp1 INTERACT POLYG/ s3 O0 ?9 g+ L1 O1 P* p7 I) R
) ^+ s" g" T+ p3 u: g
// connect statement
. C d4 V8 h. K7 ZCONNECT metal1 c2poly BY pl2co
& l4 T4 ?% T4 m& {7 e9 _CONNECT metal1 tndiff BY pl1co
( A' C# g8 ^# x7 t5 ~3 Y* jCONNECT metal1 poly BY pl1co
, f/ n! Q2 u ^9 j% [CONNECT metal1 tpdiff BY pl1co4 E* B% I7 q& I# ]
CONNECT metal2 metal1 BY VIA18 q( J- u( ?. V/ m5 ?% V
CONNECT metal3 metal2 BY VIA27 `! r# {* X% |
CONNECT metal4 metal3 BY VIA38 Q, b" ]. u4 h
CONNECT metal5 metal4 BY VIA4) g3 S) _8 e' a% a h6 R1 p) o* ]
CONNECT metal6 metal5 BY VIA5- n0 @1 v& [* O2 h7 w
CONNECT metal7 metal6 BY VIA6
$ |8 U2 Y/ R% t, y2 u+ Q* }$ C7 XCONNECT metal8 metal7 BY VIA7% t c8 _5 P8 x4 I
CONNECT metal8 CTM_M7 BY CV7# h4 k1 n3 c' j1 s5 y8 I
9 j: w% k0 S" P0 [// device definition
! `% [. f$ `' U* X L- j! [DEVICE MN(nmos) nmos poly(G) ndiff(S) ndiff(D) psub(B) [6 R6 K2 U7 ?# L: L& ?
property W,L% A, e3 Y! u; [
W=(perimeter_coincide(nmos, ndiff ) + perimeter_inside(nmos, ndiff)) / 2
3 T/ p% U+ O3 D% T3 Q* t L=area(nmos) / W h- @* M V! g3 h8 B
]* A, x y2 m% B# ]( l- }6 Y M0 D
; E& u6 k5 ~; y5 ~7 s
// trace property
5 B( k: \* G' D; a _1 i, qTRACE PROPERTY MN(nmos) L L 0! h# Q( G) q7 b; z
TRACE PROPERTY MN(nmos) W W 0 |
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發表於 2008-7-23 16:34:23
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