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發表於 2010-10-27 17:23:41
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4.Are there any special thermal management concerns when using Stacked Silicon Interconnect technology? 6 d: H! N; }- N, P b
No. Because the interposer is passive, it does not dissipate any heat beyond what is consumed by the FPGA die. Stacked Silicon Interconnect technology FPGA devices are, therefore, comparable to a single die if such a large monolithic device could be manufactured.
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5.Is Stacked Silicon Interconnect technology reliable?
7 r, @ b9 U! i" N& m6 jYes, in general, internal stress of Stacked Silicon Interconnect technology package architecture is lower than the equivalent size of monolithic flip-chip BGA package since the thin silicon interposer effectively decouples any internal stress build up. Therefore, thermo-mechanical performance improves by reducing maximum plastic strain in the package.4 e7 S( S, Y5 {. n( M3 @" ?
" }# h2 G$ t3 C( k8 U7 U* I6.Who is expected to use the FPGAs made with the Stacked Silicon Interconnect technology?
; j, a) w1 ]7 f6 g/ A$ NCustomers in Communications, Medical, Test and Measurement, Aerospace and Defense, High Performance Computing, and ASIC prototyping (emulation) who are looking to implement their next-generation, most demanding applications with FPGAs are likely to benefit from the earlier availability of the most resource-rich FPGA devices. By not having to drive off-chip through I/Os (parallel or serial), across PCB traces to adjacent FPGAs, designers that have previously used multiple FPGAs in their system will appreciate the high-bandwidth, low-latency, power-efficient interconnect between the FPGA die. |
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