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0. Check circuit topology and connectivity.
: Z; [/ P' U3 c3 B C5 S; f" kThis item is the same as item 0 in the DC analysis.
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1. Set RELTOL=.01 in the .OPTIONS statement.
% ]+ u( Z, {% f& PExample: .OPTIONS RELTOL=.01
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: ^. v. a7 ^! _$ J- q! L+ k8 l( S2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.
# R, v( U6 ?* r1 B. g& FExample: . OPTION ABSTOL=1N VNTOL=1M
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3. Set ITL4=500 in the .OPTIONS statement.$ q; a) P9 U M8 [$ J% x9 r) c
Example: .OPTIONS ITL4=500& R3 s$ @0 s: _/ m- k6 b
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4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance.
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5. Reduce the rise/fall times of the PULSE sources.
1 ?6 }- S8 T$ }8 |1 yExample: VCC 1 0 PULSE 0 1 0 0 0
" f% T; `% d2 ]: H' A/ m$ m T# @becomes VCC 1 0 PULSE 0 1 0 1U 1U
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, o* A+ A* x! r& _! P: Y5 D7 M6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources." F4 ?* Q+ `& D1 r$ [
Example: .OPTIONS RAMPTIME=10NS
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7. Add UIC (Use Initial Conditions) to the .TRAN line.3 n2 k) ~' O1 U2 s6 k
Example: .TRAN .1N 100N UIC
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8 F+ D, ^4 ~! s: o+ ?8. Change the integration method to Gear (See also Special Cases below).
3 L* k9 r$ R0 u5 Q+ D+ _0 `& yExample: .OPTIONS METHOD=GEAR |
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