A Layered Verification Approach Applied to an AMBA-Based System

phoenixfeng

It’s common knowledge that the verification
stage for a given system is
5 c+ |- b( V4 z5 D4 karound 70% of the overall design
effort and schedule time. Reducing
overall time spent in test creation and
- d* Y1 ^9 i3 Gdesign verification is a high priority.
Success in these two areas increases
9 S2 f8 \* ^1 y' Q5 t: Tproductivity and helps deliver products
7 x" l2 {4 t) |' s& y8 g. Gto market faster. To achieve these verification
goals, engineers are constantly
looking for new and innovative ways to
( M( t, f2 A6 A$ c/ n- Z& b/ M8 e; U. oconquer the verification challenges that
( v1 \; e6 r- W- \3 g& rface them.
0 u$ m" @# `' F0 [# `7 ^% K. [- l0 NThis article discusses a layered verification
/ N& B7 g/ {4 l' R" y' Lapproach as applied to an AMBAbased
system component. The layered
' V4 s; i$ h$ d  H3 _8 L3 Iapproach is used to create a standardized
verification environment that can
adapt as the design challenges
increase. Typically, reuse is very high
within an AMBA-based system because
8 e2 j/ l, \7 B3 n9 Q* U7 Kmany new designs are based on earlier
versions of the standard system. The
example shows the layered approach
being applied to verify an individual
' t5 z$ w: S' d# K& U8 rblock as well as its integration into the
: {: l6 ?2 _3 J4 p- {subsystem and final system representation.

femark

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