|
Analog / Mixed Signal Examples0 O3 }1 Q: T) i* B& ]1 D4 K
: j8 [0 F* G7 e- e x: N& h
Behavioral Models of ADCs3 E' ~/ h6 q6 n9 s! s/ D
\ams\sampling\; sampling_101;- e& @$ M( L6 o( {: I2 a* J+ \
Sigma-Delta ADC 1st order modulator $ cd \ams\adc\; dspsdadc2; 5 u2 ~) e' S6 `' ?
Sigma-Delta ADC 2nd order modulator $ cd \ams\adc\; dspsdadc3;
6 O4 B# F' K$ O$ o" f9 q, ` Sigma-Delta ADC 2nd order modulator discrete time (switched capacitor prototype) $ cd \ams\adc\; dspsdadc4; ; ?1 Z& r/ F3 A# E# {3 N8 B0 b
0 O! Z% J2 R# Q- a! E" _Behavioral RF
0 J' ^1 M) b2 D( ] d, F7 E Measurement of Lowpass Filter Freq Response $ cd feed_fwd_2;
. W: w3 l* A) `9 r! T& N& n5 u8 m
! I0 M+ s1 S) v! rPLLs
% b8 [7 _, F# C2 B VCO with phase noise $ cd
2 Q. U$ R3 i W- A Pll with freq domain instruments $ cd \ams\pll; & x; H9 B2 g: }9 @( f2 }, ?1 {6 x
Pll fractional with analog compensation $ cd \ams\pll; + }' I3 x# }/ i# \
Pll fractional with digital compensation $ cd \ams\pll; . }1 _7 p3 j2 x7 w+ s! k
Pll optimization (Nonlinear Control Design) $ cd \ams\pll; ) N3 x2 j( y, n/ H$ f: l4 o6 `" g
Carrier and Symbol Timing Recovery (NCO->ADC) $ cd \ams\pll; carrier_timing;
' }) R! n* v3 ]8 \/ O) K4 s# E Carrier and Symbol Timing Recovery (Fractional Delay) $ cd \ams\pll; timing_recovery_1; |
|