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0. Check circuit topology and connectivity.. [: h5 T' a1 {2 ?9 c4 c4 ~
This item is the same as item 0 in the DC analysis.
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' j8 R" z) o, U7 P! J1. Set RELTOL=.01 in the .OPTIONS statement.+ P, }% D, n/ z p
Example: .OPTIONS RELTOL=.01
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. R; o* L( {# g7 R2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.
$ k8 }7 e" _8 k; R1 ~6 D+ GExample: . OPTION ABSTOL=1N VNTOL=1M3 a( e$ }; x* E! e- R2 z7 s- O
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3. Set ITL4=500 in the .OPTIONS statement.2 r+ n/ W0 X" Y
Example: .OPTIONS ITL4=500; r9 f( w! Y- p- o! p! C
2 m& S, E) j; p2 L" {% N4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance.0 q. H0 Y2 m! C7 T3 {/ y0 U/ d
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5. Reduce the rise/fall times of the PULSE sources.: J7 v* H% D2 t" x- Y
Example: VCC 1 0 PULSE 0 1 0 0 0; B7 e: O' [% Q5 o
becomes VCC 1 0 PULSE 0 1 0 1U 1U
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6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources.+ J- ?: ?( j4 q
Example: .OPTIONS RAMPTIME=10NS
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7. Add UIC (Use Initial Conditions) to the .TRAN line.- k+ @8 r$ a! n8 f* Z1 B3 o
Example: .TRAN .1N 100N UIC: v' h8 P/ K) k; ~: S: `8 \/ {# [
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8. Change the integration method to Gear (See also Special Cases below).) V8 Z% H) ~3 I
Example: .OPTIONS METHOD=GEAR |
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