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Senior ASIC engineer
客户 a start up company with innovative technology
* x) ]& C5 k& f% g地点 Shanghai% \, \4 a" v5 X+ z* }( `
* ?$ m( a6 [8 u职位要求
% M3 Q' Y7 ?. B' J/ r5 + years experience in ASIC design -> must % h8 o ~$ W9 ~# @ `
· MS in Electrical Engineering (or equivalent) is a must have4 t4 ^% g! ]2 Q, C9 w
· Experience with WIFI baseband/MAC or related wireless baseband technology desired -> plus
" Y& S/ A: A6 V; S( w! j% _· System on Chip (SOC) Integration Experience, including AHB/AXI, CPU integration -> plus
8 t, k. M7 ~3 L6 z; L1 E' c· Experience with interfaces such as SPI, SDIO, USB -> plus
, Z% @4 t2 a$ _7 u% G7 }· Working knowledge of networking protocols such as TCP/IP, 802.3, 802.11 -> plus3 @4 N& D$ u2 k% } [
· Must be expert in Verilog RTL language -> must% s8 z( ^* C: }# a A+ m
· Must be familiar with the ASIC design flow from RTL through synthesis, including the tool flow. -> must
* g0 t, |6 a( s$ K6 s2 N· Verification experience – Verilog, System-Verilog, Coverage Analysis -> must for verification engineer, plus for design engineer* S" c: j0 [# E3 ^1 Y4 s/ K/ i
· FPGA emulation experience -> plus. o- b, t m# f
· Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging -> plus/ d3 o" T, m2 R6 u0 T
· Experience with digital backend |
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