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最近使用一塊自行layout的版子,上面有FPGA與DSP共同運作,希望透過FPGA加速DSP運算,
- w+ y+ v3 q' O( }+ M但是當FPGA當中有燒錄程式時
8 E3 r$ W/ e ]5 Y; t; o* a- l1 UCCS會告訴我要 reset emulator,DSP的程式就無法繼續執行4 \( P" j1 z- `
不曉得這大概會是甚麼樣的問題所造成的?) h2 k& z1 y B# C0 y+ ?1 y
$ R& l# s# [- rFPGA跟DSP的EMIFA的所有腳位都有連在一起/ V0 m# j4 y0 J- e9 N) @; @
DSP是用6414,FPGA是EP2C35,CCS版本是3.1- j" z. Y9 h6 t) ?/ X
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CCS丟出來的錯誤訊息如下:8 S! J8 m( }2 J; {5 V5 p6 M% l
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Trouble Halting Target CPU:
$ _: t2 H* n9 Y( _' g+ I' }. IError 0x00000020/-11514 f9 T/ ^2 M# W2 m
Error during: Execution,
4 h6 W! L. ?) ]/ a, Z- i$ g Z6 EProcessor communication timeout.
; l* T1 Y" a0 FIt is recommended to RESET EMULATOR. This will disconnect each target, $ s! r. V; S' \8 ?8 y
perform an emulation reset, and then reconnect each target.8 i" i- r& D) |; K5 }' L
Power cycle the target board before continuing.
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# l; {8 L/ i. D1 ?, R6 D- k[ 本帖最後由 guesswho461 於 2008-5-2 04:37 PM 編輯 ] |
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