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Single end--->單端輸入(從P端輸入)% o+ i" D2 D' ]6 t' y
Differential--->差動輸入(LVDS,,等)$ C' ?4 i+ Q/ }* g
如果CLOCK頻率不是很高,可採單端輸入GCLK pin,再從內部去除出所要的CLOCK頻率.( S# |. X; g1 r s
5 h# L6 U# Z; T7 ^. n0 `: [若要用DCM,從Xilinx Architecture Wizard(在ISE Accessories--->Architecture Wizard)去自動產生所要的CLOCK頻率.Wizard 會產生 .vhd,.xaw,.ucf檔.把.xaw加入design.(利用ISE add source)以下是以單一個DCM instance作例子.
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( Z3 ~4 \1 E" H: |: ?+ d: xEX: (輸入75MHz--->>輸出50MHz)% R4 T" [8 _! h% o1 o8 e
entity ClockManageris
7 X2 y) K n L) X4 b$ r: {Port ( clk_50mhz : in std_logic;9 L5 q( E$ h, ~8 ^6 ]! y4 I! A
clk_75mhz : out std_logic;
/ ~/ U7 O4 o5 I: \) X+ c# ^$ `3 hclk_75mhz_180 : out std_logic);, E! n D. O3 F$ e+ D4 d s9 A
end ClockManager;
8 E D/ A( S0 Y6 E8 w! jarchitecture Behavioral of ClockManageris; B& e& ~+ G+ T2 e
component clkgen_75mhz
! n* v/ r8 t9 T! n+ nport ( CLKIN_IN : in std_logic;4 X e5 ~: m+ V" d8 y# c
RST_IN : in std_logic;; S C6 l2 B; K; m8 K, V" _
CLKFX_OUT : out std_logic;9 C% ?8 a* h3 ?% I2 Y
CLKFX180_OUT : out std_logic;
; R( u5 A$ U1 N. g5 fCLKIN_IBUFG_OUT : out std_logic;4 a8 ]1 `* W- z6 A3 l: H5 ]
LOCKED_OUT : out std_logic);
' ?% g/ E1 b9 W% H' f Yend component;: C8 }5 f% z* x2 }, ?
begin
# J& \+ n: ?9 l- jgen_75mhz: clkgen_75mhz' X' e8 F7 \& A, p
port map( CLKIN_IN => clk_50mhz,
' M6 u2 V& F) H* g# b* j: MRST_IN => '0',
. u X; W5 I7 D0 \3 B KCLKFX_OUT => clk_75mhz,
$ [# H% |# L0 L$ _6 I/ X/ o) _' P4 l* `CLKFX180_OUT => clk_75mhz_180,
% j6 ~4 A/ @& fCLKIN_IBUFG_OUT => open,
. j0 r- \' D3 ]9 ?3 mLOCKED_OUT => open );& k# `* {, @% W( {
end Behavioral; |
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