Month
/ f8 _0 m: E5 E | Topic
) d1 \$ ~4 ~7 f6 [! d+ V3 v% }3 } |
January5 ~+ N+ P) g+ D' q
| • Parasitics & Parasitic Extraction% ~" P- F) [7 [, S( w6 Q
|
February+ v; ]% {4 u1 P6 ?
| • Verification Methodologies & Tools
! T4 ~) e. i4 R) L. W' v, _• CAE/CAD Tools for FPGAs
! s& L$ m: j5 u. S% \$ t |
March3 r4 O* n& Z8 |1 H* Z
| • Configurable & Reconfigurable Processors
4 Z0 I3 o4 j0 _5 U& ]1 J |
April
) S2 h1 N+ A6 f) y4 g c* t | • Hardware/Software Co-Design
. Y( T* }- v! p/ ?6 B- f, j• On-chip Interconnect, Network on chip (NoC) 0 j! z; L2 e7 V$ |
|
May" s/ I/ \4 f4 C0 Q
| • Electronic System Level Design (ESL)
" ~& o/ f; b( t0 e* o+ V" Z |
June
% }, E6 V! s# r9 J" N" U/ n | • Timing Analysis, Closure, & Sign-off- ]0 p* d: O; u
• Low-power Design Methodologies & Tools0 y! j$ B9 ^1 u
|
July% w! Y5 z5 C+ M
| • FPGAs in DSP Applications. [8 t1 f8 n+ {- @; M/ p
|
August
u" T: L1 p7 ]9 G9 V! h7 Y4 V | • Formal Verification Methodologies & Tools2 z) M' z$ e! x0 L) h
|
September7 O2 d, I! F+ x9 R- R
| • Structured ASICs & FPGA-to-ASIC Conversion7 q: ^( ^# @- ]. U5 ^9 w1 R
• Design-for Manufacturing/Yield (DFM & DFY)
# [$ D S6 ~8 U7 k; J |
October Y0 i, g. B3 H3 y
| • ATPG, BIST & DFT; M b$ J* @. n6 B& @* N
|
November
* A; N% o) x% z; W | • Physical Design (Partitioning, Floorplanning & Placement, Routing, Optimization)0 d9 L9 k5 a' v- l8 T) Y/ a, s
• Device/Circuit Modeling & Simulation9 A) N3 h2 L0 J/ r$ Y
|
December
, y2 f- z2 f* N6 u | • Analog & Mixed-Signal Design
, c& |8 s* w/ ?# ?2 I9 _ |