Month
) A% W/ n9 q3 S | Topic
( f9 Y; G5 W6 ~! W2 ] |
January
* J# K6 d0 k2 m' J0 f- ^ | • Parasitics & Parasitic Extraction
; _9 ^# |8 i7 t2 X; U/ I" n |
February
4 b+ R* O8 O$ q: ~, E& f$ T | • Verification Methodologies & Tools
- S8 M5 ]6 c! h! A6 C8 e• CAE/CAD Tools for FPGAs. W+ ] T$ I3 N- H' o `/ m, q
|
March
! J# n! u- N# B7 z. ] | • Configurable & Reconfigurable Processors# \2 R& J+ ^) `: \: ^
|
April
* N) i5 Y7 H m/ q | • Hardware/Software Co-Design
# `) |0 a$ q- S5 |, O( a( ^• On-chip Interconnect, Network on chip (NoC) 5 z3 e% I* u# t. I: z p
|
May
2 S4 q, ?) x; _# }# G& r | • Electronic System Level Design (ESL) p' w% V1 K! x
|
June
/ M& `4 s3 {% \1 n | • Timing Analysis, Closure, & Sign-off
) c+ x3 p7 U4 t" x! U• Low-power Design Methodologies & Tools
" r/ ?5 }. q/ `8 b% x |
July- A) i# {% M) L: c' Y1 }/ \
| • FPGAs in DSP Applications
1 n, p% G; E7 i. V |
August W- J% q- o7 }0 {
| • Formal Verification Methodologies & Tools! t, n! T3 N9 c* f/ m; {: \
|
September& E$ R7 h2 k/ L5 ^3 [
| • Structured ASICs & FPGA-to-ASIC Conversion) k8 o8 p( V1 h; f1 |
• Design-for Manufacturing/Yield (DFM & DFY)
+ E; q( q$ u% d4 \ b5 V: f |
October
2 X% c3 B* N% s6 ?- v | • ATPG, BIST & DFT
3 o" t, N7 {- A4 ~2 [' d2 i |
November0 q, v2 d9 J. L$ Q( h
| • Physical Design (Partitioning, Floorplanning & Placement, Routing, Optimization)
1 ^7 I+ b6 e! `( Y& K7 A+ Z* j• Device/Circuit Modeling & Simulation
/ J1 t+ q5 l+ q, K: z; i0 y' } |
December
Q% Q3 M# w G5 } | • Analog & Mixed-Signal Design
$ p0 {1 t W' P0 Z" o+ y2 x5 V8 O |