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回復 #1 tom218 的帖子
問題不夠清楚哦?????要VHDL還是Verilog??? 8bit的count有很多種,要up count還是down count?????要有加reset還是....????
# j& w Z& t9 }我給你幾個參考.
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VHDL count
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7 t4 D5 f7 s- u! d! i0 Oprocess (clock, reset) 1 k. z, o# k2 J O1 c$ g: `
begin( p8 {7 V1 l7 [0 c0 Z1 ]
if reset='1' then 1 m4 a0 d& S, F( V: f8 F
count <= (others => '0');
0 C& n' {( W5 p elsif clock='1' and clock'event then
" _7 s# P6 G9 p if clock_enable='1' then1 d) ]9 ~; p$ R5 G0 v/ j9 _ @
count <= count + 1;
6 s( a$ x- } C$ E: Y d end if;$ I [# I) r' }; M# d% Z$ \
end if;
. ~; v$ j( n- G9 ^end process;* `% _; B( F% N& s* M" V+ L6 i/ i
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Verilog count5 R3 x9 Y/ R2 l
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reg [7:0] count;
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4 ?* r- _# n$ {! p, w* \- t always @(posedge clk)) t! }9 f+ v/ @" E) w8 D
if (clock_enable)
4 i6 z" `5 H. {) t) [- a count <= count + 1;' G& r% n6 J7 J# U. e( q
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VHDL比較器$ E4 _, }0 F% B& W. N
process(clock)
: V9 k. s, \, G$ y8 q5 Vbegin
( e( g- D; b, Y+ |, J, _! P- v if (clock'event and clock ='1') then # t& _( m% p6 `9 E
if ( input1 > input2 ) then
A' x9 z D- ~' M J' [. e output <= '1';
/ [* j8 E) s, I' h! S; {1 D else : l' O; A' G; j9 v0 p4 A
output <= '0';
. p! R6 c8 {( K2 Q7 c k end if;
8 C- Z3 u3 U& @4 k end if;
# ?! ^6 l3 X" A" J9 U2 G$ |- N+ Pend process;
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5 O) j4 W" X' Y0 s+ v3 o0 T" p, j7 xprocess(clock)$ l4 O3 T4 P6 A j3 q" Z
begin
. B$ {8 u" |& w4 Z if (clock'event and clock ='1') then . o! v& O+ I" @& e& H# I# F
if ( input1 < input2 ) then
: I+ T4 r$ {+ H1 R* Z; a: r, W2 O output <= '1';
J" Z: b2 L( d: ^0 U- M else # E8 Y4 l4 G3 ~
output <= '0';4 j0 W6 G, ], h! y" ]7 H
end if;+ k* M. A6 ?4 {$ J. H5 y
end if; , S( t0 Z/ D0 t0 r
end process; " l4 Q3 Q* i2 z- ?# C4 q
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Verilog比較器
( E$ i4 B" w1 E5 O" ireg output;
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always @(posedge clock)
: J0 u2 k% q9 l9 O/ ~3 t5 z if (input1 > input2)
+ L) ~ g: H, E3 V ?6 p& m output <= 1'b1;, q7 P8 @ x& N
else
5 h9 h0 F" P( b output <= 1'b0;( [( j$ c: y9 a! W- s4 ~2 E
( t- A: W0 Y# D! c5 t( o# A2 z3 K. Yreg output;
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always @(posedge clock)
# e: P- N" J) @: U6 X if (input1 < input2)7 p& j# T a8 I+ p0 t# \5 e
output <= 1'b1;
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output <= 1'b0;
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希望有幫助^_^ |
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