FPGA verification Engineer most difficult job functions?

ranica

招聘公司：A fabless IC design company
招聘岗位：系统产品经理
5 c0 g7 A) q1 B0 V  H7 I) _! r工作地点：Beijing

岗位描述：
主要职责： 定制芯片的实际应用方案，为客户提供具体系统应用的解决方案，统计芯片在应用中出现的问题并形成改进建议书。
9 u. h7 G' |1 n) K
3 X! b( r6 r' c5 N& `2 h: }+ v# v职位要求：
; Q! ~" A6 z7 S. P职位需求： 1. 计算机、通信、电子工程类专业，本科及以上学历。英语CET-4级以上水平，良好的英文读写能力； 2.了解民用消费类产品的框架结构及应用领域； 3. 具备较强的芯片级理解能力，对高速视频接口（LVDS, DVI, HDMI, DP）、数字电视相关芯片有深入的研究或应用，可以很准确的知道芯片的指标含 义和解释； 4. 熟练掌握 Cadence或PowerPCB/Powerlog ic等软件，熟知原理图设计，PCB 的布线规则和产品的生产流程。能够独立调试系统板级硬件； 5. 具备敏锐和快速的反应能力；良好的思维能力、信息收集、分析能力； 6. 良好的团队合作意识和沟通能力； 7. 适应经常出差，勤奋刻苦，爱岗敬业； 8. 具有较强的嵌入式软件编程能力，熟悉LINUX系统的应用。能够独立调试系统系统软件； 9. 具有产品应用及管理经历者优先。

ranica

招聘公司：A famous IC company
招聘岗位：SoC System Verification Engineer
( ?3 K6 @' n: b2 j2 Q+ v工作地点：Xi'an

岗位描述：
Job Description: * Defines and develops system validation environment and test suites. * Hardware System Validation of Baseband ICs and peripheral for Mobile Terminals Technical coordination possible depending on experience and skills * Functional verification of the baseband IC and analyze of the occurring problems * Definition and implementation of test cases for the different modules(HW/SW, Low level drivers, Linux drivers) * Lead internal customer support during the evaluation phase * Interface to Concept Engineering Team, Design Team, SW Team

ranica

职位要求：
: I3 L0 F1 a& D) r: N& NJob Description: * BS. or MS. Degree, MS. preferred, in Electrical / Electronics Engineering or equivalent * Minimum 2 years experience with the following tools/domains are recommended: * Knowledge of Embedded system * ARM Tools (ADS), GCC know how * Script languages (GNU Make, Make, Make File structures) * Debug Tooling Multi-ICE, Lauterbach, OS-aware debugging * RTOS Symbian, Nucleus, Linux or equivalent * Usage of C models (Virtual Prototype) to test Software before silicon availability * Configuration Management (Versioning Tools: ClearCase) * Knowledge of the following cores/architecture concepts are recommended: * ARM 7/9/11/Cortex Series and all controller functions: Interrupt/DMA... * Multimedia concept: JPEG, MPEG, Camera, Display, Multimedia Card Storage devices... * Standard Interfaces (UART, SSC, I2C, USB HS, USB FS, USB HSIC, MIPI HSl, SlimBus, MIPI Unipro¿) * Memory devices (DDR1, DDR2, SDRAM, Mobile RAM, NAND and NOR Flash) * Connectivity functions: WLAN, BlueTooth, GPS, FMR... * Good English, Excellent communication skill and team spirit oriented

ranica

招聘公司：A famous IC company
招聘岗位：Digital Design Engineer
8 L  P" o: W2 T. G4 z4 B& _工作地点：Beijing

岗位描述：
Duties · Digital design, including synthesis, timing simulations, power optimization, DFT · Mixed signal design; and verification · Define, develop, and implement characterization, test plans, test vector generation · Work with other division test groups inside/outside FSC to identify possible co-operative opportunities to optimize test solution · Work on the design of analog blocks like voltage regulators, I/O buffer, output drivers, voltage references, oscillators · Work with product definition; characterization, and test engineers in the full product development flow; Work with application & test engineers to define optimal design and characterization solutions, based on design objectives · Layout floor planning, including P&R, DRC, LVS, and LPE
3 z' A: a# D* v0 E+ D, C4 g/ S. b
$ q5 `5 U1 T5 S! I8 F( x职位要求：
! L+ s. T; r# v0 rRequirements · Minimum 3 years direct digital IC design experience · Minimum 3-5 years direct mixed signal IC design experience · CMOS mixed signal circuit design and proficiency with industry standard design tools and Verilog/VHDL · Knowledge in CMOS/BiCMOS Analog circuit design Experience in Cadence IC Design tool set, simulation, verification · Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus Team-based, cross-functional organizational structure experience preferred · Excellent written and oral communication and presentation skills · Satisfactory written and oral communication skills in English · MSEE degree or above or equivalent experience · Strong communications skills; written, verbal, presentation and listening; · Good interpersonal skills to work in a team environment; · Good command of written and spoken English required; · Excellent interpersonal, written communication and presentation skills

ranica

招聘公司：A famous IC company
0 X1 `" g9 U' n8 x招聘岗位：Sr. Design Engineer
  f* m7 L# {. h" B- `) \工作地点：Shanghai、Beijing
2 E' z0 k9 P0 c0 G/ s; z- B
岗位描述：
Duties · Analog IC circuit design, simulation and verification · Design analog products and blocks such as high current or high capacitive load output drivers, operational amplifier, comparator, voltage reference, oscillator, error amplifier, voltage regulator etc. · Design of the switching power IC, DC-DC converters, for mobile/portal application · Evaluation, simulation and analysis of power architectures and circuit topologies · IC layout including floor planning, DRC, LVS, and LPE · Work with application and testing engineers to define optimal characterization and testing solution · Work with product definers and product engineers in full product development flow
6 P1 H' J7 C6 l, |. e% `
职位要求：
) }6 u& l6 X/ A/ eRequirements · Minimum 5 years direct DC-DC IC design experience, with MSEE or above degree · Strong knowledge in analog CMOS and Bipolar IC design · Working direct experience with switching power supplies, DC-DC converters, Battery charger, and their various topologies · Theoretical understanding of the power electronics, switching power supply topologies · Prior experience with power management related IC design a strong plus · Knowledge in analog IC layout · Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus · Excellent written and oral communication and presentation skills · Satisfactory written and oral communication skills in English · MSEE degree or above or equivalent experience · Strong communications skills; written, verbal, presentation and listening; · Good interpersonal skills to work in a team environment; · Good command of written and spoken English required; · Excellent interpersonal, written communication and presentation skills

ranica

招聘公司：a top 15 semiconductor company
( |+ |; l2 j  v9 G4 @4 X招聘岗位：Product Engineer
工作地点：Beijing
8 Y& p9 |! @1 n8 z. h$ J
. S7 N. k4 f) P: q  \岗位描述：
, O0 s9 Q4 ~+ B- Design database verification by simulation and on FPGA - Chip function evaluation - Develop test firmware and tools (Hardware and Software) - Develop evaluation board - Cooperate to debug chip issues - Customer support • Assist with customers’ issues • Visit customers and provide on-site support • Build up demo system

6 w/ O; U: g& [# _职位要求：
( m! e/ y( p. \3 x2 C' I2 E- BSEE or above with minimum 3 years communication system experience - Familiar with Verilog. Has digital design experience with Verilog in real project - Minimum 3 years FPGA working experience, including code writing, timing analysis, debug - Familiar with at least one of schematic and PCB layout tools - Excellent English skill will be required. - Strong inter-personal, teamwork and communicational skills

ranica

客户 A famous IC company
地点 Shanghai
3 `: M, g. G! L3 T8 p& z5 M6 ~
职位描述
We are looking for a person to join a design team to execute a state-of-the-art IC design project in the wireless communication field. Candidate must be familiar with digital IC design flow with a proven record of design and verification of a complex design project that led to successful silicon. Proficiency in Verilog is required.

" o/ L6 K/ w9 C3 o6 f- `2 i* |9 f职位要求
Experience in the following areas of expertise is desired:
' o, ^7 r, {$ sWireless media access control (MAC) design experience would be highly desirable
Knowledge of TCP/IP and DMA Offload Engine design experience will be a plus
RTL design, verification, and chip integration
Experience in the following is beneficial but not necessary requirement:
Communication systems and RF systems
% i7 i# a; l6 SFamiliarity with wireless communication systems and standards (802.11b/g/n and WiGig)
Knowledge of interface protocols such as PCI/PCIe would be a plus
9 _  g# {- u7 ^& g; L+ U* hFPGA design flow, testing, and emulation bringup
" u! A' D, h$ d( ?6 V6 n$ [. U
, o+ y- W, h: S+ A& iOther requirements:
Familiar with design and verification languages, EDA tools and ASIC/SOC design methodology
Good script language skill, such as Perl, Tcl and Shell
# O7 e7 n" Z. B9 N* \9 `Good written and oral communication skills in English
Good Team player
Candidates must have MSEE degree with at least 5 years of experience

ranica

招聘公司：A famous IC company
) T7 K3 g9 N4 C$ f! `招聘岗位：高级ASIC设计工程师
. W. i4 X. K7 t3 l. W: v" S工作地点：Shanghai
6 r. T4 U7 P; s9 \; q
岗位描述：
1、定义设计模块结构并编写芯片设计规范； 2、使用VHDL/Verilog编写逻辑模块的RTL代码； 3、编写测试向量对模块进行仿真验证； 4、在FPGA平台上进行芯片级的测试验证； 5、进行模块级的芯片综合与时序分析； 6、编写完整的设计和验证报告。

% ^" g3 `2 `# A/ t5 w1 r职位要求：
" V6 k( T8 T: b+ y7 Z' G: {2 X1、具有电子或通信工程类硕士以上学历； 2、 熟练运用Verilog/VHDL进行芯片前端设计，熟练运用设计仿真综合和测试工具，如quartus，Xilinx，modelsim，nc，debussy，逻辑分析仪，信道仿真设备等； 3、深刻理解数字电路设计和时序分析方法，并拥有故障定位和解决问题的能力； 4、深刻理解通信原理、数字信号处理等基础知识，熟悉无线通信原理与常用算法； 5、具有3年以上芯片设计经验，拥有无线通信物理层开发项目（如DTMB、CMMB、DVB、3G, LTE等）经验者优先； 6、工作认真严谨，积极上进； 7、良好的团队合作意识和沟通能力。

ranica

Verification Engineer
# ]* J- B  M% O, |
公      司：A famous IC company
工作地点：上海
2 k5 c2 S) ?$ M6 _; `2 r5 ]
The Role:
·         ASIC  verification
; V' W: K5 U/ R4 A4 V8 @/ a$ [·         Work closely with the California teams
·         Support chip tape out and bring up

Requirements:
·         3+ years experience in ASIC Verification
·         BS in Electrical Engineering (or equivalent) is a must have, MSEE is desired
·         System on Chip (SOC) Verification Experience, including AHB/AXI, CPU, Interface integration verification
·         Very familiar with verification languages – Verilog, System-Verilog, and VMM
, f/ y2 w( k  T1 f. ]·         Test plan and test case documentation
0 i7 N* Z' I$ ]% i1 r1 ~1 s·         Functional coverage and code coverage analysis
: N3 O! G7 w3 I" W·         Must be familiar with various scripting languages used in verification, including Perl, Csh, Make, etc.
·         Experience verifying interfaces such as PCIe, Ethernet, DDR, USB
2 w! Y( n0 M: i# o·         Working knowledge of networking protocols 802.3 and 802.11, especially Medium Access Control and TCP/IP
- A: o0 F3 s8 E; M·         Working knowledge of C programming language
·         Must be familiar with the ASIC verification flow from feature identification to test bench development and through final tape out sign-off
0 ^2 R* X5 x. v) [6 Z( W( E·         FPGA emulation experience a plus
·         Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging

ranica

ASIC Digital Verification Engineer
公      司：A mobile chipset semiconductor company
工作地点：上海
& C0 }8 T! u; o; @9 ~
Responsibilities:  
! _0 M+ c+ g2 y& @# l( u3 `  Make verification plan for one module or whole chip.  
9 |4 a2 V" {9 e% |5 T  Build up and maintain module-level and chip-level verification environment  
# e9 @7 ^/ k, E1 b8 c  Verify ASIC digital design based on case list, and output verification report.  
* Z3 u% ~' z4 k' _+ N( t6 i6 W: o  Also responsible for lint checking and formal verification.  

4 n" H9 r! O: p$ u+ v: uQualifications:  
' M+ i  p  {) ]& c  Proficiency in logic verification.  
  Experience with Verilog logic design language.  
# o1 F2 K6 t; T  s$ b  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.  
1 M3 K* X/ F  d& C4 w  Experience with UNIX/Linux simulation tools such as IUS or VCS.  
  Experience with C and C++ is a plus.  
( e$ v7 v# Y9 g5 `8 ~! ]2 {  Experience with C_SHELL, TCL or PERL is a plus.  
  }3 a- S6 p( n8 ~! s/ `  n  Experience with UVM, OVM or VMM is a plus.  
  Good knowledge of SOC design is a plus.  
* \5 m/ x: S8 j( t5 [. J0 c  G  Good knowledge of software design is a plus.  
) u3 g1 p0 P9 c. X3 G: M  Self-motivated and good team player.  
" P2 W' b5 C. a( B" v8 i  MSEE or BSEE with 2+ years.

tk02561

Hardware Applications Engineer–Graphics
公      司：A famous IC company
工作地点：上海

Desirable
Strong understanding of microprocessors
- m; j4 p! p2 A6 VA good understanding of the interaction between software and hardware
5 w3 F2 \$ r7 \! A+ V& o/ ZUnderstanding of FPGA or ASIC implementation flows (synthesis, scan insertion, layout)
7 Q6 q/ O+ l& b) l& R- U7 WC/C++, assembler coding or other programming skills.
6 s% z! _( a; f8 s0 C, b* d1 }Knowledge of GPU or graphics processing specification, like OpenGLES, Direct-X, is preferred

% D4 W: ]/ Z' g; Y4 W4 t& o) h+ q. yJob Requirements：

tk02561

Education
0 O. u* ]9 [+ Y0 c! }Good university degree, in Computer Science or Electronics Engineering ideally, although other science graduates would be considered if they have relevant experience.
  
Experience
0 a1 e2 P6 U7 p) I2 h  d' A  d, YMinimum of 4 years industrial experience
, ?& b0 R( W- `6 B6 R3 cExperience or knowledge of FPGA or ASIC design, simulation and/or verification techniques, including RTL coding and simulation, in Verilog or VHDL
Experience in integrating SoC peripherals
Experience of interacting with colleagues outside of China
9 S: `. W, B" O2 \2 ?5 qProfessional experience of customer and sales interaction
2 J! V6 A% s9 a; J* fDemonstrable experience of problem solving and debug skills

. p: V# |: f0 o- ]$ g, PPersonal Requirements
Must have excellent written and verbal communication skills with both colleagues and customers, including good written and spoken English
$ V$ s5 V0 [5 U( C* E# LMust be proactive in obtaining engineering or management input, in order to complete project and internal tasks in a timely and accurate manner
Must have the desire and ability to solve problems quickly
. N/ q4 Q: k' U3 o# p# MMust be enthusiastic and well driven
) f; P/ W  D, j% v. EMust be able to schedule own workload and plan tasks – based on both internal and customer requirements.  
: n/ L% k3 H' M# LMust have good inter-personal skills, and be able to work well within a team; especially when under pressure
: V& E  S+ v2 i0 ~Must be willing to be flexible and accept new challenges
& ~. K/ J2 E- W' i7 U/ ~, \$ S4 f' d0 oMust be able to travel on a regular basis, both to give customer training and also for internal business reasons.

ranica

Senior Digital Design Engineer
) S! t* i4 M! n8 x公      司：A leading semiconductor company
1 l+ }  m: p8 _; L0 _工作地点：香港

) Q9 i+ j8 ?$ {Job Responsibilities:
# Y  S4 A( a) _5 x    Perform logic design, RTL coding, design verification, logic synthesis, DFT and static timing analysis
( g: ^+ A; s# O" C& m    Develop verification environment and coverage closure
2 T6 a2 ?% u  v. k8 |" }7 u" L: v    Support wafer level testing and silicon evaluation
* K" Q7 I8 ^. |! f& x, b7 |    Prepare technical documents
% ]( j" ~. E+ U( G, A. K
; r; V; }% ^0 vJob Requirements:
    B.Sc or above in Electronic Engineering or equivalent. Applicants with postgraduate degree would be considered as an advantage
  f! ]' o# P( r5 A6 O1 Q    5 Years or above of solid experience in one or more of the following areas: Verilog-based logic design and synthesis, constrained random    testbench with System Verilog & UVM, assertion based design verification or circuit-level SPICE simulations
    Knowledge of SoC and embedded system.
    Knowledge of scripting languages such as Perl, TCL and Make
; y, c8 G3 `& M  ^3 o    Candidate with less experience will be considered as Digital Design Engineer

ranica

数字IC验证工程师
公      司：A famous IC company
- |4 B8 X! D# @! ]+ S工作地点：上海
2 s+ B1 G' H' p3 G- K9 M
岗位职责：
/ ^1 @7 Z4 ?! M9 _0 W% ]( L( C1、负责整个团队验证平台的搭建、维护
2 f4 g% K- \# e, X2、先进验证方法和验证平台的评估、导入
! U& j" f8 a7 w: D* b) B- G3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。
* H7 y( Q9 @& w
; R% k* [+ v/ ^: p2 P7 O职位要求：
! a3 l& T" L% q1 e4 V1、大学本科及以上学历，电子、通信、计算机或微电子专业；
2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础；
3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等；
& ^/ c, H/ }' n$ I& ]3、有1~2年芯片验证的相关工作经验；
4、具有较强的学习能力、沟通能力和良好的团队合作精神；
5、有基于ARM处理器的SOC芯片验证经验者优先考虑。

jcase

数字IC验证工程师
6 b+ F6 j/ X7 j: W6 j公      司：A famous IC company
工作地点：上海

- a9 Q; M, z9 {$ n7 s2 U岗位职责：
( l5 x' W% a, e+ C1、负责整个团队验证平台的搭建、维护
2、先进验证方法和验证平台的评估、导入
4 m, Z7 O0 S1 R2 s2 u: W3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。

" F; n$ y3 d) [6 \# w9 O职位要求：
" P7 O( e9 d4 Z: U6 W1、大学本科及以上学历，电子、通信、计算机或微电子专业；
2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础；
3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等；
# F  R4 S# T" j: U3、有1~2年芯片验证的相关工作经验；
4、具有较强的学习能力、沟通能力和良好的团队合作精神；
5、有基于ARM处理器的SOC芯片验证经验者优先考虑。

ranica

Senior Digital Design Engineer
) u2 m; a3 @* R" F2 B公      司：A famous European IC company
工作地点：上海
  @; b* g6 r  h9 O  [
Job description  
- G3 j; Q% Q0 p" Q- define system partitioning of s/c circuits and system  
0 Y, b0 h+ w' l% j% K* c- define HW/SW co-partitioning  
0 n, v  V  S6 f/ B. R- |1 A- provide technical feasibilities based on system simulation and/or FPGA based demonstrator  
5 e2 F* Z% q0 E8 }- propose new technical solutions on s/c and system level  
- design digital part of mixed signal (smart power) ASICs  
- close cooperation and interaction with international teams  
- coach junior engineers  
, i% }* [: v; y' ~# X1 n; N6 r* Y
Required knowledge competencies and attributes  
- master degree in microelectronic circuits or systems, Communications, Computer Engineering (or equivalent)
- > 5ys experience in digital design  
- good understanding of ASIC mixed signal flow (Cadence based)  
5 }) N9 g6 [4 s+ Z3 Y- strong background in HDL coding, verification and toplevel integration  
, n9 H7 Z# q- K; }- good understanding of communication interfaces used in Automotive (SPI, CAN, LIN, Flexray)  
# a4 x/ p4 o0 e( ^6 c; f' v) M- experience in FPGA development  
1 J) \* R  o/ c- very good communication skills (written, oral)  
- self motivated and high level of flexibility  
1 p# U' Q. V, K8 W- foreign languages: English, German (not a must)

sophiew

数字IC验证工程师
9 K+ {  H% t# T& n0 {& d- x2 y公      司：A famous IC company
工作地点：上海
9 s5 e6 _7 ?, t: N0 ]* m8 w
岗位职责：
( k* |$ b; @5 E3 e" k1、负责整个团队验证平台的搭建、维护
2、先进验证方法和验证平台的评估、导入
4 s; ^9 w. D9 r8 l, b3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。
3 q$ z/ G# t6 y" a4 e3 r, M
1 O2 f9 Q: p" J% U" x+ k职位要求：
. P+ V0 S9 m% E& e3 ~4 p1、大学本科及以上学历，电子、通信、计算机或微电子专业；
  b! p* p7 A8 o2 O% n# G2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础；
3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等；
3、有1~2年芯片验证的相关工作经验；
4、具有较强的学习能力、沟通能力和良好的团队合作精神；
5、有基于ARM处理器的SOC芯片验证经验者优先考虑。

ranica

ASIC Verification Engineer (WMAC)
公      司：A famous IC company
7 J$ f' X* q" g0 K5 z, U0 ?工作地点：上海
- q$ X8 T  H; `; g' x
# j  h5 B6 z8 g/ y8 ]/ O2 E+ G1 bThe Role:
; l( S& ?' w/ q        ASIC design and verification
, u' P0 }8 f! G/ w- u. I        Work closely with the California teams
$ H( @$ w6 t) ^, g) B        Support chip tape out and bring up
: o2 ]( s6 k6 z* S+ `% |, z% Q$ w
Requirement:
        8-10 yrs. experience  
. C8 w: B2 y( ~6 ~1 z        Knowledge of Verilog / System Verilog & Perl
        Has worked on complex project; experience with 802.11 is preferable
# p, @% n) V  D: O5 b2 O" o        Can work independently - want him to take over MVE
6 [* a1 q! [' a6 S        Experience in Networking SOC, Ethernet MAC or any other MAC layer protocol experience is plus

ranica

ASIC Digital Verification Engineer
  k4 S* p& v2 ~# z& M公      司：A mobile chipset semiconductor company
工作地点：上海

Responsibilities:  
  Make verification plan for one module or whole chip.  
# z' R5 u' _: T( V, d# H( c, `  Build up and maintain module-level and chip-level verification environment  
  Verify ASIC digital design based on case list, and output verification report.  
  Also responsible for lint checking and formal verification.  
& C: ?1 T8 u. B$ d
: v0 w( d7 k6 e  KQualifications:  
  Proficiency in logic verification.  
$ ~/ t/ I, l6 ~1 a1 S  Experience with Verilog logic design language.  
3 Z4 y6 p3 w# ^8 R1 [. _% b# M  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.  
0 k7 Y" n0 \+ [" a. V  Experience with UNIX/Linux simulation tools such as IUS or VCS.  
; P& D9 X& ?& X" X( J  Experience with C and C++ is a plus.  
7 r$ E7 v4 K; K& o4 X: K/ b  Experience with C_SHELL, TCL or PERL is a plus.  
  Experience with UVM, OVM or VMM is a plus.  
2 x% J8 f5 E, c6 u  N. G/ Z$ k6 C  Good knowledge of SOC design is a plus.  
  Good knowledge of software design is a plus.  
  Self-motivated and good team player.  
  MSEE or BSEE with 2+ years.

ranica

Staff Verification Engineer
, [' [1 X0 p7 _8 C  v% H公      司：one famous IC company
工作地点：上海

Qualifications
% |7 e  g( `4 k7 LMS in EE/CS/ME.  
' O1 ]7 @$ d/ Q+ a4 {' \3 j( UMinimum of five  years experience.
0 S5 {% K# k7 gAdditional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
  V  v3 ~. J( ?Candidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
1 D- I( i( P/ v( F8 g' R: NCandidate should be familiar with industry standard ASIC design and verification tools and flow.
4 V* [! }7 l. U* u$ n6 }Good knowledge ddr protocol and computer system achitecture would be an added advantage.
) Q- b0 H* `  H0 {$ UGood knowledge of Perl and shell programming would be an added advantage.  
/ `' r! ?7 D" x- R2 x! K
Responsibilities:
-Understanding the expected functionality of designs.
-Developing testing and regression plans.
-Designing and developing verification environment.
-Running RTL and gate-level simulations/regression.
-Code/functional coverage development, analysis and closure.
5 T8 w6 U7 B& e, I, h
3 W1 u: x5 Y" X2 J5 M) VRequirements:
7 c# ]: W% A+ lExperience & Skill: 5 Years
-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
, [6 w# a5 }7 M) q-Knowledge in ASIC/FPGA design process and verification tools.
1 @, h9 O' a3 z" R1 N6 n  |2 {$ q-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
- Scripting and automation skills (tcl, perl, makefile etc) a plus.
-Familiar with C/C++.
; L6 M3 C5 t& F4 u$ `/ P; H8 \% i-Knowledge of DDR protocol a plus.
-Independent and self-managing.