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//可直接透過synthesis tool用於PLD,FPGA不可 LUT delay則要採其他方式。$ V. d- u; W7 A! B* W4 D% V0 Q/ c
//所有註解都要保留
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; R, d7 g, F) Q) Y' ``timescale 1 ns / 1 ns( o0 {: M, T% U: j0 {
module xclk(sclk,ena,set,outp);
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input sclk,ena;8 b% G3 L8 h* a4 F o8 y
input [1:0]set;
4 ]" A5 D2 {& P A7 f7 m8 }output outp; , n/ D8 j# x/ Z1 P6 ~
9 Z- q2 v( z0 G! a/ awire outp;+ _5 u3 k/ N9 j7 Y7 @. F
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/**** Node preservation for nodeA **************/
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1 z4 ~( _/ |, @! A//exemplar attribute nodeA_5 preserve_signal true/ j" Y/ w) d0 V) t+ k
' \; ?: z- `0 p6 ^- a5 G//exemplar attribute nodeA_4 opt keep
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0 }) `; |; A6 j5 d# C/**** The following comment form also works ****/( F2 g, J% @# V) ~" d8 u
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//exemplar attribute nodeA_3 preserve_signal true4 n2 C) `# }: I$ ^" G
% z$ c f7 d5 D6 I0 ]; y//exemplar attribute nodeA_3 opt keep/ D7 E$ W: P5 r: x- W# u6 X
2 |' q. M, |+ d# y$ a7 c6 v/**** The following comment form also works ****/
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% I8 L6 L2 b) I% ^& T- n//exemplar attribute nodeA_2 preserve_signal true& j" J, l6 W# O- V8 Q8 {' A
+ s" {' Q5 [, C8 A9 o0 [& E1 n0 \//exemplar attribute nodeA_2 opt keep) S) b; A4 P) ~' W* @+ T5 W: s- _
5 D! P7 {. o, X" s/**** The following comment form also works ****/
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" s3 `: ^. K: @//exemplar attribute nodeA_1 preserve_signal true
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- n% f4 @8 a: z% Q2 v//exemplar attribute nodeA_1 opt keep8 t3 p( K" W3 g! \! p4 v+ c
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* C: ?9 |# {: z5 W0 \' E5 \/**** The following comment form also works ****/
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/*exemplar attribute nodeA_0 preserve_signal true
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exemplar attribute nodeA_0 opt keep*/
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% j/ y5 m5 h9 r0 Jwire nodeA/* synthesis syn_keep=1 opt="keep"*/;
z6 M3 g1 q! \wire nodeA_0/* synthesis syn_keep=1 opt="keep"*/;2 |+ l5 e( E, [1 g+ N
wire nodeA_1/* synthesis syn_keep=1 opt="keep"*/;
7 @" j3 Z$ a, M, `( v% @5 owire nodeA_2/* synthesis syn_keep=1 opt="keep"*/;5 q! X+ m5 o6 p$ o* J& P+ Z) Z
wire nodeA_3/* synthesis syn_keep=1 opt="keep"*/;7 K9 ~9 H( N) q& ^2 l0 e
wire nodeA_4/* synthesis syn_keep=1 opt="keep"*/;
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& L" B, M6 F) c3 `4 lassign#1 nodeA_0 = sclk & ena;
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, f7 F1 f. f/ \# o+ xassign#1 nodeA_1 = ~ nodeA_0;
0 J7 D5 c( ]( Passign#1 nodeA_2 = ~ nodeA_1;, K0 S- e( E% b* \8 R# L
assign#1 nodeA_3 = ~ nodeA_2;% R; D+ ]) v2 o8 o$ P; n* |
assign#1 nodeA_4 = ~ nodeA_3;* M/ s. @3 d2 |* V
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always@(nodeA_1,nodeA_2,nodeA_3,nodeA_4,set)& v, S2 t+ x- v: t' T. k$ @
casez(set)- Y/ P$ p' j; O/ ^7 v. k. w
1: xout =#1 nodeA_2;
+ ]2 b9 o. P2 R7 C; N7 G 2: xout =#1 nodeA_3;
& H% h1 }8 Y( t 3: xout =#1 nodeA_4;6 r7 A2 w8 m% R3 q# p
default: xout =#1 nodeA_1; u* h6 ^, `0 G' u' R9 G
endcase1 `" ]8 ^# f4 F4 S* ^" R
! I6 S. x1 F/ H u) fassign#1 nodeA = xout;; N5 n* e' k: X/ Z
assign#1 outp = ena ? nodeA^sclk : 1'bz;
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" ^: a) q: [2 S- S/ z' zendmodule
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! ^& j- j4 |4 g0 r8 F! `' X`timescale 1 ns / 1 ns' A# G% j J% ]5 A
module xclk_tf();4 q* G* T3 Z+ d
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// Inputs' R0 b1 f* Y' A
reg sclk;- p0 |. ]9 A+ I8 c* b
reg ena;
* k( i; E, `. o7 s1 @" B/ ~) a reg [1:0] set;5 t7 `: P/ k6 S* C- ?# P# k
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// Outputs2 C/ D, x0 J$ ^
wire outp;
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xclk UUT (" v8 ~+ ?: w, f, H" ~$ w3 m' v
.sclk(sclk),
$ B [5 Z% c8 J( o2 E .ena(ena), 5 u; O& ~3 W/ J
.set(set), . C* H2 j& ~, i$ h, L9 ^! x. ]
.outp(outp). Z! x7 _& {# H; [- G
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sclk = 0;$ z! r* u+ r1 Q0 V3 w
ena = 0;: Z5 Q, I7 q& g+ U! M2 B0 N
set = 0;
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4 z: _) K, E; H$ o2 Walways# 5 sclk = !sclk;& P0 |" a( C. m. F/ `
6 Z- [5 \0 m0 }- G$ ?initial begin
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# l. a0 P( _& j9 x ena = 1;9 w6 W% \ U2 [
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set = 2;
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set = 3;
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$finish;
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endmodule // xclk_tf |
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