身為IC設計者，我面對的最大壓力？

chip123

8月中旬有兩天整以「如何搭起設計除錯與結果分析之間的橋樑？」為主題的IC設計研討會，如果部分會員們有意參加，在那之前何妨先來討論討論如何？

1 ^1 Z% v7 X# N' u3 X5 x2 Zhttp://www.maojet.com.tw/Events/index.asp?Page=1
: G6 {' T7 |  }+ }
引言回覆:
IC 設計的大小與複雜度，對於產出良率與產品上市時間影響甚鉅。設計者除了要面對更為嚴苛的設計工作之外，還必須同時承受時間上的壓力。
! o; y- r" u( s0 i& q# [
$ K" Y4 v5 F8 Z$ s. v% ^" B即使運用現有的分析工具，在設計除錯與結果分析之間，還是隱約存在一道看不見的鴻溝。就算是針對 Spice 模擬工具的需求，將解決方案與看起來 “還算不錯” 的波形分析結合在一起，依舊不能有效消弭這段差距。完美整合的 “最頂級” 解決方案，不僅使用容易，更可支援以下三類資料的分析作業：模型建立（Modeling）過程中所描述之模擬、硬體量測，以及系統階層。

+ W9 O2 ^. v1 P: z7 }_________________
鏈結IC創新價值鏈，擴大IT市場同心圓
論壇需要大家踴躍的參與才能不斷的發展
休息是為走更長遠的路，回覆是發表的原動力

masonchung

壓力有部份來自EDA跟不上製程進化的腳步
更新EDA太貴,只好冒險用舊版的EDA TOOL
5 R" T) W( M  q或是Gate-count太大,擔心目前的EDA無法勝任最佳化的任務
例如 90n 的製程 到底要搭配啥版本的Synthesis和Layout tools?
3 a8 A" [& O# o$ ]' ~. Z9 c有誰清楚呢?

ryanchen

這個問題還真的不是三言兩語就可以說完
& e6 u6 v, B: l8 R
其實與其說是壓力, 還不如說設計上遇到的核心問題是如何讓模擬的數據更貼近真實的情況
比如說多 channel OPAMP output buffer 如何能保證輸出電壓的一制性?
如果是單純 pre-simulation 看起來是會一樣的
% d/ m% c# F) B2 N但如果考慮真實的情況, layout 怎麼 lay 才會 uniform ? 單顆 OP 如何擺 ?
$ D& b; ^4 t0 _$ J9 O不同 SLOT 又如何保證 uniform?
/ U8 q+ z, S1 k% j. g或許 EDA tools 看可否加入製程參數的變異係數下去跑, 以類似統計的方式來看大致上會落在哪個區域,
5 _0 B& ^! t3 i+ X5 y% H這方面就得 Foundry 是否願意提供這方面的資料了 ( WAT ?)
+ O1 Q2 Y2 g3 Q, P* q小弟想請教大家一下, 這樣的構想可以實行嗎? 若有的話如何去做呢?

tommywgt

我認識的一家service company還在用Apollo layout 0.13的ic, 超猛的, 根本是靠經驗在做事嘛...

masonchung

太猛了吧
9 B0 C2 M3 o% [5 J" A7 \7 aGUC 還是 Fararday?
* _0 b" ~' L1 ^! N5 o3 x8 NApollo是.25時代的 後來不是改成SE 和ASTRO了嗎?

tommywgt

一家不太有名的公司啦, 名字還是不要亂報好了
4 b. B- _! {# \/ ?7 ~astro是apollo的下一版
SE是cadence出的...二個不同家

[ 本帖最後由 tommywgt 於 2007-2-11 03:49 AM 編輯 ]

tommywgt

3樓的大大
你的問題要不要去ANALOG區PO看看
, M  q: _; D: [: B我是做pure digital的...

jimy

那家會不會是創X啊?
pupu 土法煉鋼

tommywgt

回到原本話題...
身為IC設計者，我面對的最大壓力？

應該是回家面對老婆或者是女朋友(要加個s嗎?說不定老婆也要加個s )吧....哈...我來搞笑,

yhchang

主要是要克服 高層的腦袋所思維不合理的 Tapeout Deadline吧
一個新製程  居然壓 3個月 做出來
真是虧 董事長想得出來
3個月後 連LAYOUT都還沒開始動工
8 i6 W% c; j) D$ \: q最後一共DELAY了半年

innoing123

(20130422 08:25:47)現代人生活忙碌，常常轉個身就忘記剛才要做的事，或者是注意力無法集中。這是因為生活壓力大，或是大腦同時要處理的訊息太多，所以造成短期健忘的現象。短期健忘只要適時紓壓、調整心態情況就會改善，但真正的失智與健忘有怎樣的區別呢？記憶力退化的人，是否也會有罹患失智症的可能性呢？4月28日熟年誌特別邀請天主教失智老人基金會社工主任陳俊佑先生到西門町的Somebody cafe，與您分享如何自行檢測並預防失智，讓您知道失智症是否已經找上您！本次講座規劃限量贈送大腦保健體操ＤＶＤ及照顧者使用手冊，歡迎讀者踴躍參加！

- _7 P! s% b/ z. {% e4 t主辦單位：出限文創有限公司&《LifePlus熟年誌》
* F! u9 O0 @& ^; @2 P% p% q協辦單位：天主教失智老人福利基金會
聯絡電話：02-2311-2371
1 s: H2 z9 l1 L; }/ z- G, t活動地址：108台北市萬華區西寧南路131號2樓(Somebody cafe)
活動網址：http://www.facebook.com/SomebodyCafe26
文化部指導

訊息來源：出限文創有限公司

ritaliu0604

客户 IC设计公司
地点 Shenzhen
, B/ {- n2 n# [3 a) v5 p
* h& w. ^7 ?  @  a- h" L& {职位描述 Responsibilities:
$ V9 ?. k3 _1 |" M3 E" Z  T5 f1) Provide support and trouble-shooting to designers for EDA tools.
2) Help to construct customed in-house analog and layout design flow
3) Maintain and update EDA tools for analog and layout design.
4) Help designers to use new features in EDA tools, or new EDA tools.
/ P8 u8 Y9 k( ^5)Maintenance of PDK and all design librarise
# H1 l6 u2 n. O) V
职位要求 Requirements:
1) At least 2 years of CAD or IC design relative work experience.
* Z( ~. t, w( O, \. O9 U) X  w2) Capable of using C language, Cadence Skill language and Perl.
" M% y0 i! M/ M% g3) Familiar with EDA tools including Hsim/Hspice/Spectre, Virtuoso and Calibre.
- a) P' k! G& k9 N2 H4) Familiar with analog and layout design flow.
5) Familiar with SOC design flow is a plus.
% ~; {# P  o& E( N4 {8 B# B- ^6) Experience of circuit design or layout design is a plus.

ranica

CAD Engineer
8 s$ W5 p1 I! B* ~客户 IC设计公司
; n0 d  Z6 B6 \; u" G+ M& Z地点 Shenzhen
8 N9 z9 B, S( f
- N7 i) g2 _; Z5 ?' z2 j2 JResponsibilities:
( k7 J7 t; b# g% o' {1) Provide support and trouble-shooting to designers for EDA tools.
2 ~* |" L$ L, w, p* ?- P; O$ q" }2) Help to construct customed in-house analog and layout design flow
! `0 O/ Q/ Z4 _0 A3) Maintain and update EDA tools for analog and layout design.
4) Help designers to use new features in EDA tools, or new EDA tools.
  V! H8 l, v$ M  v% v5)Maintenance of PDK and all design librarise
7 ]& N; ^9 z6 a4 I) X+ A" w
Requirements:
8 f" Y5 s' \4 d' h1) At least 2 years of CAD or IC design relative work experience.
2) Capable of using C language, Cadence Skill language and Perl.
3) Familiar with EDA tools including Hsim/Hspice/Spectre, Virtuoso and Calibre.
8 N2 K/ I( k0 b4 x- P4) Familiar with analog and layout design flow.
" |. T$ D, o' {( C  T5) Familiar with SOC design flow is a plus.
6) Experience of circuit design or layout design is a plus.

ranica

电路设计工程师
客户 High
7 |- V; Q, B6 j+ @地点 Beijing
  J" I+ ?9 |# h" w. Y( y3 B/ I: a9 i
" m, V; d5 r# }3 ~# ]* a# ?3 u工作职责与具体内容：
负责模拟/定制电路模块的设计，包括电路设计，仿真，版图规划和布局并指导版图设计，提供模型，流片回来的测试等。
7 V) t6 a* h2 T+ j% ?
4 l/ B' \: q( q" Z8 a职位技能要求
·熟练使用主要的EDA工具，如virtuoso,hspice,hsim,spectre等；
·有以下IP（其中之一）设计经验并成功留片：PLL，高速IO，ADC，电源管理模块，SRAM；
·良好的中英文交流及文档书写能力
·具有良好的分析问题，解决问题能力及团队合作意识；

工作经验
2年以上工作经验, 具有扎实的CMOS基础知识

学历/专业
8 g: t' [2 ]; ?2 @9 GE.E硕士学历

ranica

Staff PnR/CAD Engineer
9 s9 Z# A- M7 H公      司：NO.82-A famous IC company
5 j+ E7 E1 e1 e$ _工作地点：上海
9 O4 Q5 x' T/ ]% W; w# i7 c
Responsibilities
1.        IC Place and Route for designs up to a few million gates in deep sub micron technology, with advanced low power flow; Timing, Power, IR drop and Noise analysis
' m: z' P8 D1 x+ H9 f" s1 M- \2.        DRC/LVS command file, rule deck and chip tape-out handling and support;
3.        IC-CAD tool and design flow support

% ^3 Q' s. K1 y/ ?. T6 MMandatory Skills
3 N4 v: t" b  D. p6 S& P! Q* d1.        Place and Route in deep sub micron technology; timing, power, IR drop and noise analysis
( X5 a. r6 i6 |) U1 s. _2 o. J& m2.        In depth understanding of IC layout and command files, IC process flow
3.        Good knowledge of Linux/Unix and ICCAD tools
. T& k7 @1 v0 P% q, U8 t. _4.        Good knowledge of digital and analog IC design flow
5 d2 E! J+ h2 D5.        Scripting language and file/database conversion techniques
6.        Fluent in English

Preferred Skills
1.        IC hand-crafting layout design
2.        VLSI design and verification
  L1 A- S3 W5 q3.        Library design and characterization
2 R* N' [: ^% y2 X7 g$ q; z9 {
. M" y$ @. F& x' G, Y1 h- rEducation
! @+ v' w6 f7 _9 m/ `3 CUniversity Degree of Microelectronics, Electrical Engineering or Computer Science,
Master degree preferred
5 D9 M3 R( [" K& l. @8 N0 _4 T
Experience
) Z! K" ^/ m( D4 K/ C8+ years of working experience, 2+ experience in US or Europe based ICCompany.
' b& f8 O% z2 Z3+ years of experience in Place and Route
3+ years of experience in IC-CAD, CAE or tape-out handling

ranica

CAD Engineer
公      司：NO.25-A famous IC company
" V3 r2 n' y- \8 [工作地点：上海
7 w! ~& \  Q3 f" R7 U3 P1 {( f6 m
Job Description:
6 j3 C0 D4 F) wProvide first-class system administration services to engineering community
Install software, apply patches, manage file systems, monitor performance and troubleshoot users’ login
" L+ g  F7 _/ d4 b+ kenvironment.
Perform system failure analysis and recovery to insure consistency and integrity of file systems.
Set up and configure hardware and software for user workstations as well as enterprise servers.
Automate administrative tasks via scripts and cron jobs
9 p) D* g/ p. u; m  {4 Y% _Liaison with vendors and support evaluating product procurement.
- d5 l: H+ @1 B% S$ r* y  T# }& jSupport main stream EDA tools’ user interface
  m. Y" D: n+ L! ?, _, f
Job Requirements:
BS degree in Computer related field
3+ years of relevant experience
8 \/ E- U$ {9 O3 QHands on experience with scripting and NIX operating system
Proficient with CAD system administration tasks
8 N/ D- \* I9 u8 Y- z3 k. Z, AKnowledge of X-windows programs (VNC, Exceed, ..) and file-sharing utilities (SAMBA, ftp, ..)
Excellent written and verbal communication skills
Fluent in English
Self-motivated, team oriented and professional ethic

ranica

CAD Engineer

! J0 q4 H; ~) F6 m4 f公      司：NO.25-A famous IC company
工作地点：上海
4 p' j9 `5 v. _
Job Description:  
5 V4 }" g0 b9 _' ^' I. `2 PProvide first-class system administration services to engineering community  
Install software, apply patches, manage file systems, monitor performance and troubleshoot users’ login  
environment.  
Perform system failure analysis and recovery to insure consistency and integrity of file systems.  
Set up and configure hardware and software for user workstations as well as enterprise servers.  
Automate administrative tasks via scripts and cron jobs  
Liaison with vendors and support evaluating product procurement.  
Support main stream EDA tools’ user interface

Job Requirements:  
- s1 d4 h- M( c& S$ C- P5 A  T" {BS degree in Computer related field  
3+ years of relevant experience  
/ a% q% \' i* K- i6 lHands on experience with scripting and NIX operating system  
Proficient with CAD system administration tasks  
9 G+ {) R  @: X% RKnowledge of X-windows programs (VNC, Exceed, ..) and file-sharing utilities (SAMBA, ftp, ..)  
Excellent written and verbal communication skills  
Fluent in English  
" r! e% j( q1 T+ x6 u! w4 `Self-motivated, team oriented and professional ethic

ranica

Lead Implementation Services Engineer（Shanghai）

公      司：NO.73-One world top EDA company
4 h- x2 t  G* t6 ?工作地点：上海

, V/ V5 l1 J# A. a! L5 H职位描述
! h$ l; M0 L/ z: Y: m) _9 n% u/ W2 l1.Ability to handle large sized design implementation tasks & architectural tasks alone.  
2.Ability to assess Customer''s Design environment, to understand his application needs & to build new Design environment based on specifications & available Cadence tool technology.
  B4 I2 J0 H" w, C8 Y3.Ability to acquire a basic understanding of the (services) business environment of Cadence within 1 month.
4.Working on multi person projects of varying complexity, working especially in a multi-site/multi-cultural project. The latter requires good communication skills in English.  
5.Feeling responsible for technical delivery as well as business development & opportunity creation. Behavioral competencies: Teamwork; Customer focus; 6.Accountability; Communication; Coaching & feedback; Employee development; Leadership.
& d9 r7 T( s+ \5 b# P! |' h* J
职位要求
/ ?2 q# U& R9 r1.BS degree with 10+ years of applicable experience, MS degree with 7+ years of applicable experience in electrical engineering, microelectronics.
2.Essential that the individual demonstrates strong communication, verbal and written, and project management skills.
3.Requires good communication skills in English.

ranica

Staff/Senior CAD
9 G; w2 ]; Y5 N" f% a公      司：A famous IC company
8 E2 Z. c# g5 q0 W4 c2 J工作地点：上海

Job Duties:
% `# x- F# ^! m' ^8 M; MThe candidate will collaborate with Sunnyvale CAD team to support Shanghai design center.
1)         Industry leading edge ASIC design flow and methodology development
2)         Design tools/script development to improve design automation and productivity
3)         EDA tools evaluation, license set up and upgrade
4)         Work with EDA vendors to solve design flow or tool issues
5)         Design database management and maintenance
/ U* [! Y/ U" }/ I( N6)         Local engineers working environment support and Linux/Unix servers/system support

Qualifications:  
) N( c( p/ }0 D9 k9 x-           Experience on CAD support for digital/analog/mixed-signal IC design
-           Familiar with IC design flow related EDA tools (Synopsys, Cadence Mentor, etc.) setup under Linux environment
-           Working experience in license set up for EDA tools, version control tools and bug trace tools
) J: n0 Q" v6 @; Z. @4 X2 @-           Excellent script languages skills for internal tool development, such as Perl, Tcl, Shell, Skill and Python
: W4 ^9 m' e4 F: [# F6 v-           Experience in Pcell development is a plus
7 t  I# ?# J3 A* h  Y) |. S-           Customer oriented, good communication skill
3 a. o$ B( ]0 T* W* }-           B.S. Degree or above in Electrical Engineering or Computer Science. Major in Microelectronics is a plus.
. K' H/ ~) ~8 s2 f& F9 `+ x-           At least 3-5 years CAD experience in IC design company
-           English language skill in writing and speaking.

ranica

CAD Engineer
( W0 V$ q& d& ]7 P: \
7 t; ^! s5 v& ~' s- x7 A公      司：IC设计公司
8 X! i) A3 m1 t/ U" a工作地点：深圳
" m5 L. l1 J3 I& A
Responsibilities:  
1) Provide support and trouble-shooting to designers for EDA tools.  
2) Help to construct customed in-house analog and layout design flow  
. B# ^* b+ D% @& D. B; b7 X5 g3) Maintain and 修改 EDA tools for analog and layout design.  
4) Help designers to use new features in EDA tools, or new EDA tools.  
5 ~4 J) ]0 r- O7 m: d0 }$ I5)Maintenance of PDK and all design librarise  
  
. R* k* ~8 \) e* G3 N9 aRequirements:  
1) At least 2 years of CAD or IC design relative work experience.  
3 _! N, [( h4 g' H* G; [2) Capable of using C language, Cadence Skill language and Perl.  
3) Familiar with EDA tools including Hsim/Hspice/Spectre, Virtuoso and Calibre.  
; }, Y& V" q( P5 c" Q4) Familiar with analog and layout design flow.  
7 w1 z7 }$ u' C9 z; Q5) Familiar with SOC design flow is a plus.  
- N; s: V  y0 W+ t- R/ s5 U6) Experience of circuit design or layout design is a plus.