FPGA verification Engineer most difficult job functions?

ranica

招聘公司：A fabless IC design company
2 L" E4 N: x% v, G* L招聘岗位：系统产品经理
& b! G. u6 v. w4 a# V工作地点：Beijing

岗位描述：
: N) a/ ~- _" {' F8 c7 ~主要职责： 定制芯片的实际应用方案，为客户提供具体系统应用的解决方案，统计芯片在应用中出现的问题并形成改进建议书。

2 B( U: @+ R) v' T" u8 W0 m职位要求：
$ w# q5 C: b% P; ?' H) M职位需求： 1. 计算机、通信、电子工程类专业，本科及以上学历。英语CET-4级以上水平，良好的英文读写能力； 2.了解民用消费类产品的框架结构及应用领域； 3. 具备较强的芯片级理解能力，对高速视频接口（LVDS, DVI, HDMI, DP）、数字电视相关芯片有深入的研究或应用，可以很准确的知道芯片的指标含 义和解释； 4. 熟练掌握 Cadence或PowerPCB/Powerlog ic等软件，熟知原理图设计，PCB 的布线规则和产品的生产流程。能够独立调试系统板级硬件； 5. 具备敏锐和快速的反应能力；良好的思维能力、信息收集、分析能力； 6. 良好的团队合作意识和沟通能力； 7. 适应经常出差，勤奋刻苦，爱岗敬业； 8. 具有较强的嵌入式软件编程能力，熟悉LINUX系统的应用。能够独立调试系统系统软件； 9. 具有产品应用及管理经历者优先。

ranica

招聘公司：A famous IC company
2 X3 z0 C+ J5 m( s' o& ]招聘岗位：SoC System Verification Engineer
工作地点：Xi'an
! O) Q. X' ~3 D- R$ g
+ A0 a7 I& x+ P: ^3 J岗位描述：
Job Description: * Defines and develops system validation environment and test suites. * Hardware System Validation of Baseband ICs and peripheral for Mobile Terminals Technical coordination possible depending on experience and skills * Functional verification of the baseband IC and analyze of the occurring problems * Definition and implementation of test cases for the different modules(HW/SW, Low level drivers, Linux drivers) * Lead internal customer support during the evaluation phase * Interface to Concept Engineering Team, Design Team, SW Team

ranica

职位要求：
( m5 j: k7 v  t4 f; `3 E+ aJob Description: * BS. or MS. Degree, MS. preferred, in Electrical / Electronics Engineering or equivalent * Minimum 2 years experience with the following tools/domains are recommended: * Knowledge of Embedded system * ARM Tools (ADS), GCC know how * Script languages (GNU Make, Make, Make File structures) * Debug Tooling Multi-ICE, Lauterbach, OS-aware debugging * RTOS Symbian, Nucleus, Linux or equivalent * Usage of C models (Virtual Prototype) to test Software before silicon availability * Configuration Management (Versioning Tools: ClearCase) * Knowledge of the following cores/architecture concepts are recommended: * ARM 7/9/11/Cortex Series and all controller functions: Interrupt/DMA... * Multimedia concept: JPEG, MPEG, Camera, Display, Multimedia Card Storage devices... * Standard Interfaces (UART, SSC, I2C, USB HS, USB FS, USB HSIC, MIPI HSl, SlimBus, MIPI Unipro¿) * Memory devices (DDR1, DDR2, SDRAM, Mobile RAM, NAND and NOR Flash) * Connectivity functions: WLAN, BlueTooth, GPS, FMR... * Good English, Excellent communication skill and team spirit oriented

ranica

招聘公司：A famous IC company
招聘岗位：Digital Design Engineer
工作地点：Beijing

岗位描述：
+ |# u/ ~' {$ h6 jDuties · Digital design, including synthesis, timing simulations, power optimization, DFT · Mixed signal design; and verification · Define, develop, and implement characterization, test plans, test vector generation · Work with other division test groups inside/outside FSC to identify possible co-operative opportunities to optimize test solution · Work on the design of analog blocks like voltage regulators, I/O buffer, output drivers, voltage references, oscillators · Work with product definition; characterization, and test engineers in the full product development flow; Work with application & test engineers to define optimal design and characterization solutions, based on design objectives · Layout floor planning, including P&R, DRC, LVS, and LPE
- H; [. s  j' b  m* a# S  u: a0 d
, g# Y; [' G8 x* d职位要求：
6 B) N. i. W; W: J! }7 bRequirements · Minimum 3 years direct digital IC design experience · Minimum 3-5 years direct mixed signal IC design experience · CMOS mixed signal circuit design and proficiency with industry standard design tools and Verilog/VHDL · Knowledge in CMOS/BiCMOS Analog circuit design Experience in Cadence IC Design tool set, simulation, verification · Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus Team-based, cross-functional organizational structure experience preferred · Excellent written and oral communication and presentation skills · Satisfactory written and oral communication skills in English · MSEE degree or above or equivalent experience · Strong communications skills; written, verbal, presentation and listening; · Good interpersonal skills to work in a team environment; · Good command of written and spoken English required; · Excellent interpersonal, written communication and presentation skills

ranica

招聘公司：A famous IC company
8 ?# O# o/ Q- I* Q: K3 E. `1 p招聘岗位：Sr. Design Engineer
工作地点：Shanghai、Beijing
0 \0 |3 Z! v  j; r
岗位描述：
Duties · Analog IC circuit design, simulation and verification · Design analog products and blocks such as high current or high capacitive load output drivers, operational amplifier, comparator, voltage reference, oscillator, error amplifier, voltage regulator etc. · Design of the switching power IC, DC-DC converters, for mobile/portal application · Evaluation, simulation and analysis of power architectures and circuit topologies · IC layout including floor planning, DRC, LVS, and LPE · Work with application and testing engineers to define optimal characterization and testing solution · Work with product definers and product engineers in full product development flow
' D5 _9 h) X- ^& e5 b
职位要求：
! R8 [8 F) P! K  t6 i- ~( TRequirements · Minimum 5 years direct DC-DC IC design experience, with MSEE or above degree · Strong knowledge in analog CMOS and Bipolar IC design · Working direct experience with switching power supplies, DC-DC converters, Battery charger, and their various topologies · Theoretical understanding of the power electronics, switching power supply topologies · Prior experience with power management related IC design a strong plus · Knowledge in analog IC layout · Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus · Excellent written and oral communication and presentation skills · Satisfactory written and oral communication skills in English · MSEE degree or above or equivalent experience · Strong communications skills; written, verbal, presentation and listening; · Good interpersonal skills to work in a team environment; · Good command of written and spoken English required; · Excellent interpersonal, written communication and presentation skills

ranica

招聘公司：a top 15 semiconductor company
. v( [- C4 H3 h3 {, O7 P招聘岗位：Product Engineer
3 |9 z! j' V0 e: v& Q工作地点：Beijing
3 Z5 b/ r' H  I5 z4 l5 b" E
& J$ |( a5 Y' M' {! Y' L% I岗位描述：
+ |2 ?) r4 ]( i  @3 q- Design database verification by simulation and on FPGA - Chip function evaluation - Develop test firmware and tools (Hardware and Software) - Develop evaluation board - Cooperate to debug chip issues - Customer support • Assist with customers’ issues • Visit customers and provide on-site support • Build up demo system
0 N+ Y6 R' h& C1 ]4 y$ X
* F7 p+ @$ {$ x* w  Z1 G职位要求：
% M; K1 [( l4 w" s1 h- BSEE or above with minimum 3 years communication system experience - Familiar with Verilog. Has digital design experience with Verilog in real project - Minimum 3 years FPGA working experience, including code writing, timing analysis, debug - Familiar with at least one of schematic and PCB layout tools - Excellent English skill will be required. - Strong inter-personal, teamwork and communicational skills

ranica

客户 A famous IC company
地点 Shanghai
* G  f% ?0 g. I2 _9 i
职位描述
: N. S, @0 g0 h! D' p2 K) AWe are looking for a person to join a design team to execute a state-of-the-art IC design project in the wireless communication field. Candidate must be familiar with digital IC design flow with a proven record of design and verification of a complex design project that led to successful silicon. Proficiency in Verilog is required.
6 v( a+ s6 k( F& K. j# z# C
/ h2 W& h2 ^8 K( \+ p/ L% ^$ h/ p职位要求
Experience in the following areas of expertise is desired:
Wireless media access control (MAC) design experience would be highly desirable
: w7 D- {" Z! D: \' IKnowledge of TCP/IP and DMA Offload Engine design experience will be a plus
RTL design, verification, and chip integration
- ]0 N. k* i1 |6 V) @; u5 ^; MExperience in the following is beneficial but not necessary requirement:
Communication systems and RF systems
7 I9 H% b- x  Z* Y  c# x3 V! ^* QFamiliarity with wireless communication systems and standards (802.11b/g/n and WiGig)
Knowledge of interface protocols such as PCI/PCIe would be a plus
FPGA design flow, testing, and emulation bringup
7 t; L' O8 k0 O7 J) J9 \
Other requirements:
Familiar with design and verification languages, EDA tools and ASIC/SOC design methodology
Good script language skill, such as Perl, Tcl and Shell
Good written and oral communication skills in English
, W% W" N% A* l0 o" D4 a1 b' CGood Team player
3 E8 P' @1 @* y) L3 C+ O1 rCandidates must have MSEE degree with at least 5 years of experience

ranica

招聘公司：A famous IC company
. g* C  X9 P7 m5 {) r! p7 l- h( r招聘岗位：高级ASIC设计工程师
工作地点：Shanghai

岗位描述：
8 k, U9 {+ X; B1 T/ c1、定义设计模块结构并编写芯片设计规范； 2、使用VHDL/Verilog编写逻辑模块的RTL代码； 3、编写测试向量对模块进行仿真验证； 4、在FPGA平台上进行芯片级的测试验证； 5、进行模块级的芯片综合与时序分析； 6、编写完整的设计和验证报告。

职位要求：
% d- Z4 ], q# ?+ L, ^( P% k1、具有电子或通信工程类硕士以上学历； 2、 熟练运用Verilog/VHDL进行芯片前端设计，熟练运用设计仿真综合和测试工具，如quartus，Xilinx，modelsim，nc，debussy，逻辑分析仪，信道仿真设备等； 3、深刻理解数字电路设计和时序分析方法，并拥有故障定位和解决问题的能力； 4、深刻理解通信原理、数字信号处理等基础知识，熟悉无线通信原理与常用算法； 5、具有3年以上芯片设计经验，拥有无线通信物理层开发项目（如DTMB、CMMB、DVB、3G, LTE等）经验者优先； 6、工作认真严谨，积极上进； 7、良好的团队合作意识和沟通能力。

ranica

Verification Engineer
# u" M2 E3 M1 M6 z
公      司：A famous IC company
工作地点：上海
6 c& f! n; M/ V2 _3 ], _
* D- R% m' F2 A/ Q+ @. IThe Role:
·         ASIC  verification
·         Work closely with the California teams
·         Support chip tape out and bring up

Requirements:
, o& Q2 N# k9 U·         3+ years experience in ASIC Verification
·         BS in Electrical Engineering (or equivalent) is a must have, MSEE is desired
·         System on Chip (SOC) Verification Experience, including AHB/AXI, CPU, Interface integration verification
3 J5 \) U$ G" ^- t3 M" {; }·         Very familiar with verification languages – Verilog, System-Verilog, and VMM
·         Test plan and test case documentation
0 k. I2 U. u0 y. x  S·         Functional coverage and code coverage analysis
·         Must be familiar with various scripting languages used in verification, including Perl, Csh, Make, etc.
·         Experience verifying interfaces such as PCIe, Ethernet, DDR, USB
·         Working knowledge of networking protocols 802.3 and 802.11, especially Medium Access Control and TCP/IP
$ e7 `/ A! S% A9 t" D·         Working knowledge of C programming language
/ a# z9 M" B+ j6 c·         Must be familiar with the ASIC verification flow from feature identification to test bench development and through final tape out sign-off
·         FPGA emulation experience a plus
- W$ o4 E0 C# H( ^3 g# o0 }. R·         Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging

ranica

ASIC Digital Verification Engineer
" u: o9 L0 ^. D: C6 ~  Z公      司：A mobile chipset semiconductor company
工作地点：上海

; h7 G8 e; z8 K: y. ~' A1 \% cResponsibilities:  
  Make verification plan for one module or whole chip.  
  Build up and maintain module-level and chip-level verification environment  
/ ^, G6 C* m+ U1 k$ t/ M1 D  Verify ASIC digital design based on case list, and output verification report.  
4 n0 c7 x3 Z+ A" z9 p4 u* U  Also responsible for lint checking and formal verification.  

1 T9 r# Q" [* E- KQualifications:  
5 Y; |" \8 S) }! U$ P! U  Proficiency in logic verification.  
  Experience with Verilog logic design language.  
  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.  
  Experience with UNIX/Linux simulation tools such as IUS or VCS.  
/ D% [* O1 w$ n5 G, o) j  Experience with C and C++ is a plus.  
  r- Z# T. V& b% u/ G, B  Experience with C_SHELL, TCL or PERL is a plus.  
2 y, q. a+ _8 `1 p/ V4 w  Experience with UVM, OVM or VMM is a plus.  
  Good knowledge of SOC design is a plus.  
9 z2 e+ s8 Q2 ?) d3 v# X8 |6 w  Good knowledge of software design is a plus.  
  Self-motivated and good team player.  
' t, M- o2 \- C5 m/ s; _  MSEE or BSEE with 2+ years.

tk02561

Hardware Applications Engineer–Graphics
公      司：A famous IC company
工作地点：上海
+ e9 J+ F% D: l. ^9 O
Desirable
Strong understanding of microprocessors
  H7 V' H' e1 kA good understanding of the interaction between software and hardware
1 l9 o  z) A8 b7 S3 n! _1 a# kUnderstanding of FPGA or ASIC implementation flows (synthesis, scan insertion, layout)
C/C++, assembler coding or other programming skills.
) j& G4 c9 F6 d; e# M: M2 mKnowledge of GPU or graphics processing specification, like OpenGLES, Direct-X, is preferred

  z- {5 e: \. a3 B1 lJob Requirements：

tk02561

Education
Good university degree, in Computer Science or Electronics Engineering ideally, although other science graduates would be considered if they have relevant experience.
0 R* m1 o5 w) u* \* z9 a  
Experience
( G- D5 F3 Q, n$ bMinimum of 4 years industrial experience
! u: ?9 S2 ~+ Y6 s! M+ l  F& b4 GExperience or knowledge of FPGA or ASIC design, simulation and/or verification techniques, including RTL coding and simulation, in Verilog or VHDL
Experience in integrating SoC peripherals
) y% y: ]% {- R- A7 g4 T) jExperience of interacting with colleagues outside of China
" j' I- ]% C2 w& Q1 u+ @Professional experience of customer and sales interaction
Demonstrable experience of problem solving and debug skills

8 N  f' h; ~* `& b8 u8 {: BPersonal Requirements
Must have excellent written and verbal communication skills with both colleagues and customers, including good written and spoken English
& G6 m# B, O3 E3 jMust be proactive in obtaining engineering or management input, in order to complete project and internal tasks in a timely and accurate manner
Must have the desire and ability to solve problems quickly
/ b! A/ v8 z- rMust be enthusiastic and well driven
Must be able to schedule own workload and plan tasks – based on both internal and customer requirements.  
" \" G4 l- \7 ^" u( {% y& WMust have good inter-personal skills, and be able to work well within a team; especially when under pressure
5 C  C6 d1 F3 X3 t* QMust be willing to be flexible and accept new challenges
Must be able to travel on a regular basis, both to give customer training and also for internal business reasons.

ranica

Senior Digital Design Engineer
公      司：A leading semiconductor company
工作地点：香港

; l: H8 T5 O. q2 i& dJob Responsibilities:
    Perform logic design, RTL coding, design verification, logic synthesis, DFT and static timing analysis
    Develop verification environment and coverage closure
7 O3 Y8 ^# j* o    Support wafer level testing and silicon evaluation
! O% d6 h- n! x: u5 ^: Z; `    Prepare technical documents
' K' v# U$ f- G( \5 x
Job Requirements:
1 W6 j; C2 L/ g! J+ E    B.Sc or above in Electronic Engineering or equivalent. Applicants with postgraduate degree would be considered as an advantage
    5 Years or above of solid experience in one or more of the following areas: Verilog-based logic design and synthesis, constrained random    testbench with System Verilog & UVM, assertion based design verification or circuit-level SPICE simulations
: E0 m$ z/ Z& N* z0 T    Knowledge of SoC and embedded system.
    Knowledge of scripting languages such as Perl, TCL and Make
    Candidate with less experience will be considered as Digital Design Engineer

ranica

数字IC验证工程师
公      司：A famous IC company
  |+ b6 B, V' D: ~工作地点：上海

岗位职责：
9 q5 g& y; Y, a4 E1、负责整个团队验证平台的搭建、维护
6 m9 \& z# }( s* }2、先进验证方法和验证平台的评估、导入
3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。

! H  @+ w( n3 l职位要求：
1、大学本科及以上学历，电子、通信、计算机或微电子专业；
2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础；
3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等；
% M1 ?2 c& w) x2 p9 c. \+ D! t2 v3、有1~2年芯片验证的相关工作经验；
/ w, @6 i: u6 s  |2 `4、具有较强的学习能力、沟通能力和良好的团队合作精神；
5、有基于ARM处理器的SOC芯片验证经验者优先考虑。

jcase

数字IC验证工程师
公      司：A famous IC company
3 g7 I) o9 Y! w. V' [  j工作地点：上海

岗位职责：
1、负责整个团队验证平台的搭建、维护
+ ^2 q6 |9 F) \$ [  {3 @4 o! j4 e2、先进验证方法和验证平台的评估、导入
3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。
' \6 u3 U# A* o6 F5 Q. Q' w* T% r
$ W3 g* c$ @& U3 _9 q: I& b/ Y职位要求：
1、大学本科及以上学历，电子、通信、计算机或微电子专业；
9 W3 K4 K  o' G/ T: Y2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础；
3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等；
! O  N' @2 ~2 Y3、有1~2年芯片验证的相关工作经验；
4、具有较强的学习能力、沟通能力和良好的团队合作精神；
  x+ C' ?: M. ^) I0 U( E9 F5、有基于ARM处理器的SOC芯片验证经验者优先考虑。

ranica

Senior Digital Design Engineer
3 L3 C: V! Q$ I  w: r! e公      司：A famous European IC company
% t1 h; B- {# t工作地点：上海

: E1 o) \" r3 o4 A2 H- i6 R. y# `Job description  
- define system partitioning of s/c circuits and system  
- define HW/SW co-partitioning  
- provide technical feasibilities based on system simulation and/or FPGA based demonstrator  
- propose new technical solutions on s/c and system level  
- design digital part of mixed signal (smart power) ASICs  
- close cooperation and interaction with international teams  
- coach junior engineers  

Required knowledge competencies and attributes  
- C1 d4 k& j" Q5 L0 |: b# K- master degree in microelectronic circuits or systems, Communications, Computer Engineering (or equivalent)
- > 5ys experience in digital design  
* t: y4 B) n7 k- good understanding of ASIC mixed signal flow (Cadence based)  
- strong background in HDL coding, verification and toplevel integration  
- good understanding of communication interfaces used in Automotive (SPI, CAN, LIN, Flexray)  
6 t8 J5 J" U. p' k- experience in FPGA development  
0 p6 t; s! ]% c- very good communication skills (written, oral)  
- self motivated and high level of flexibility  
- foreign languages: English, German (not a must)

sophiew

数字IC验证工程师
公      司：A famous IC company
  H3 n, V% {1 L工作地点：上海
2 B5 \( D" U( e' H$ ~7 X
+ v1 q; [6 L, o4 w! S8 m. T岗位职责：
( v1 R8 h5 B' U$ i2 W( W1、负责整个团队验证平台的搭建、维护
! u" Z: X& L" E/ ~2 h& L( V2、先进验证方法和验证平台的评估、导入
+ }; {: R# }, p) e; q( [3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。
5 x8 m' E  m# W, ~; ]
+ ]" K% f' [% y职位要求：
+ V3 R2 P* }: e1、大学本科及以上学历，电子、通信、计算机或微电子专业；
# b  r" R7 e) L7 F5 I2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础；
0 N% k; Y- |. z9 F% A" [  [. }, ^3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等；
3、有1~2年芯片验证的相关工作经验；
/ I% [+ ^0 f1 K( }4、具有较强的学习能力、沟通能力和良好的团队合作精神；
5、有基于ARM处理器的SOC芯片验证经验者优先考虑。

ranica

ASIC Verification Engineer (WMAC)
8 v1 S, t" x% \) O0 a$ t) F& I公      司：A famous IC company
: m, @" Q: u6 [0 j/ Q+ F0 X工作地点：上海
" x& A! S4 ?8 _# h$ w. O) |3 }6 \
The Role:
* O7 P: V& c8 I1 H8 |- w* u0 j        ASIC design and verification
. N  O9 `) d- b1 Q0 d+ _        Work closely with the California teams
: Z0 p2 a) Y6 `        Support chip tape out and bring up
3 s- F' v/ c! y
Requirement:
        8-10 yrs. experience  
        Knowledge of Verilog / System Verilog & Perl
! L# q& c/ |, t, ~9 l* o        Has worked on complex project; experience with 802.11 is preferable
+ `( h0 W5 C7 C% p3 K        Can work independently - want him to take over MVE
& ~! ]5 |% q: n5 U6 Q! `% J        Experience in Networking SOC, Ethernet MAC or any other MAC layer protocol experience is plus

ranica

ASIC Digital Verification Engineer
公      司：A mobile chipset semiconductor company
工作地点：上海

$ t5 u$ ~9 a# R2 ~  XResponsibilities:  
  Make verification plan for one module or whole chip.  
1 z+ u: E* L' W( g5 @  Build up and maintain module-level and chip-level verification environment  
% }; x$ U- X0 s  Verify ASIC digital design based on case list, and output verification report.  
  Also responsible for lint checking and formal verification.  

Qualifications:  
: f+ O4 F* [! k  Proficiency in logic verification.  
  Experience with Verilog logic design language.  
  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.  
  Experience with UNIX/Linux simulation tools such as IUS or VCS.  
  Experience with C and C++ is a plus.  
  Experience with C_SHELL, TCL or PERL is a plus.  
  Experience with UVM, OVM or VMM is a plus.  
8 i  }: S" k* l( K! f6 k  Good knowledge of SOC design is a plus.  
  Good knowledge of software design is a plus.  
5 {6 Y: ~8 f# I' z* [% a  e$ G: v  Self-motivated and good team player.  
" `  r) ~: t4 N0 m  MSEE or BSEE with 2+ years.

ranica

Staff Verification Engineer
9 l0 z3 C. e+ F) V" v公      司：one famous IC company
$ [9 y; W# S) q& i+ U/ D工作地点：上海
1 t( |9 |2 {* z6 x; F
( G' \; W+ G  S4 MQualifications
  w* H! A7 ^; i: [7 E. h% X6 ZMS in EE/CS/ME.  
Minimum of five  years experience.
2 h* \$ J+ N# ~, k  q; l: WAdditional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
Candidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
6 J7 \" D/ }5 ~; E) ]& fCandidate should be familiar with industry standard ASIC design and verification tools and flow.
; m. `: ]9 ]! P) r; `Good knowledge ddr protocol and computer system achitecture would be an added advantage.
: n8 p( t. b9 h2 [4 vGood knowledge of Perl and shell programming would be an added advantage.  
2 }" M$ I6 F5 g" B* Q
5 A7 C+ R! t4 p" y2 V3 `Responsibilities:
9 I( x0 ~/ _6 l+ i# G9 t' t-Understanding the expected functionality of designs.
* c% E$ B9 |6 H-Developing testing and regression plans.
: t8 d. l: ^6 ^/ c. t( b-Designing and developing verification environment.
+ q' a; Q( K% Y& r; d+ N-Running RTL and gate-level simulations/regression.
-Code/functional coverage development, analysis and closure.
& [- ]2 [  P' \4 u2 g# \" r! f
# z) g) R" {& v  k( V: G% [Requirements:
) h; v+ [* Q) Z+ t  o% @' m4 ^Experience & Skill: 5 Years
# ~8 [, [; ]8 N  u4 V$ Q* h: d-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
; l& B  D0 f$ w3 N-Knowledge in ASIC/FPGA design process and verification tools.
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
- Scripting and automation skills (tcl, perl, makefile etc) a plus.
9 Z: |/ W9 ]0 \1 ]3 L# h3 N8 j2 G-Familiar with C/C++.
-Knowledge of DDR protocol a plus.
/ Y3 N; o8 J4 n9 D9 c' o-Independent and self-managing.