|
Analog / Mixed Signal Examples+ f& P0 M5 ]- B6 W7 K; t2 |( o
5 B: }2 n; K. J z6 q) a
Behavioral Models of ADCs2 f2 A- q/ X& W! }3 V1 l5 x4 d
\ams\sampling\; sampling_101;
9 ]( T2 F$ ]/ _. g Sigma-Delta ADC 1st order modulator $ cd \ams\adc\; dspsdadc2;
1 p( T9 `6 X% c Sigma-Delta ADC 2nd order modulator $ cd \ams\adc\; dspsdadc3; 0 b: N9 ^) @2 y& ~9 m
Sigma-Delta ADC 2nd order modulator discrete time (switched capacitor prototype) $ cd \ams\adc\; dspsdadc4;
- m$ s/ J2 t, O( |2 X, } 1 B7 r: V" f, X5 v1 n# H1 d9 Q
Behavioral RF! D* R0 g9 O" V8 o. y+ k' l
Measurement of Lowpass Filter Freq Response $ cd feed_fwd_2;
: ^4 G, _/ i: f: }- n0 I# M. I/ k1 R W1 g2 [- F% j; S/ Q) \' I: N
PLLs
6 v0 I8 e+ v: r# y VCO with phase noise $ cd
7 d1 C" K r6 w% u6 t! x Pll with freq domain instruments $ cd \ams\pll;
0 A* }' }* T4 F; ^2 _2 y- A6 u Pll fractional with analog compensation $ cd \ams\pll; ; v. Q! m6 ?& o: n3 t* R
Pll fractional with digital compensation $ cd \ams\pll;
3 _/ m! y, ~/ } Pll optimization (Nonlinear Control Design) $ cd \ams\pll;
* z- M& T$ a2 ? Carrier and Symbol Timing Recovery (NCO->ADC) $ cd \ams\pll; carrier_timing;
2 K# `1 K( p& [. |$ c7 i1 R Carrier and Symbol Timing Recovery (Fractional Delay) $ cd \ams\pll; timing_recovery_1; |
|