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0. Check circuit topology and connectivity.
# [+ E% \& J5 }7 ?- {This item is the same as item 0 in the DC analysis.
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1. Set RELTOL=.01 in the .OPTIONS statement.
8 [2 x5 O3 Z; h2 X" y; l/ KExample: .OPTIONS RELTOL=.01
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2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.7 V# R( ~/ A: l, q: c7 q
Example: . OPTION ABSTOL=1N VNTOL=1M' f: k4 |6 k8 |4 v# l) V
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3. Set ITL4=500 in the .OPTIONS statement.. L' Z; U/ w, d4 K+ W% y% Y
Example: .OPTIONS ITL4=500) v; A6 g. V1 c2 L8 x- S" D
! [( J0 V8 m* j0 `" M0 J8 M4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance." ?& S0 I% q: |7 g2 d+ J# n! _
" q! T" o, F1 h5. Reduce the rise/fall times of the PULSE sources.6 O( _% N' G8 Y
Example: VCC 1 0 PULSE 0 1 0 0 0
1 T i+ Y+ x. r& p& ubecomes VCC 1 0 PULSE 0 1 0 1U 1U
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9 z4 m% ]5 a, j: A7 V& j) O6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources.
V) ^- O, z, \5 c3 P/ _$ RExample: .OPTIONS RAMPTIME=10NS" D3 ~$ }" _3 ^/ Q
5 U# M5 o. g$ ^. ^2 c7. Add UIC (Use Initial Conditions) to the .TRAN line.8 f" B2 Q3 t$ p: V# g& C: c: ~* d
Example: .TRAN .1N 100N UIC
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) B: u) @: Z7 m4 q8. Change the integration method to Gear (See also Special Cases below).
4 \; u5 }1 ~8 d2 w3 ^5 o5 l+ I9 N5 OExample: .OPTIONS METHOD=GEAR |
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