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0. Check circuit topology and connectivity.- D9 w p; r& H& Q9 R
This item is the same as item 0 in the DC analysis., ^9 j3 }- B0 G+ d, F
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1. Set RELTOL=.01 in the .OPTIONS statement.$ R5 X1 O; x' o2 b0 n
Example: .OPTIONS RELTOL=.01
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2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.
# r9 y6 |+ D# ?Example: . OPTION ABSTOL=1N VNTOL=1M
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3. Set ITL4=500 in the .OPTIONS statement.; q4 R0 c) U/ _9 A% t9 ~# a
Example: .OPTIONS ITL4=500
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( E5 h3 ?, m9 v/ M9 S* w% g$ ~4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance.* n$ Z, _4 O+ T" K9 l/ O
2 g; H& Y1 W4 ?0 t1 Q5. Reduce the rise/fall times of the PULSE sources.3 f7 c+ M% ~7 ^/ m3 f
Example: VCC 1 0 PULSE 0 1 0 0 0
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, R( E, n1 ~3 J) T: e6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources.4 p- {' w. g- W; ?9 R2 c
Example: .OPTIONS RAMPTIME=10NS$ Y2 B7 ? t; i. T1 w# [
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7. Add UIC (Use Initial Conditions) to the .TRAN line.
) ?2 Y3 o; y/ k, ~Example: .TRAN .1N 100N UIC b. I8 [2 d7 _5 Z1 @7 k
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8. Change the integration method to Gear (See also Special Cases below).
, _# q, K3 k5 f! A) Z, ?3 X1 SExample: .OPTIONS METHOD=GEAR |
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