|
6#
樓主 |
發表於 2010-10-27 17:23:41
|
只看該作者
4.Are there any special thermal management concerns when using Stacked Silicon Interconnect technology? & E6 w+ W2 T( A. ^; K
No. Because the interposer is passive, it does not dissipate any heat beyond what is consumed by the FPGA die. Stacked Silicon Interconnect technology FPGA devices are, therefore, comparable to a single die if such a large monolithic device could be manufactured. . F j& |) D, A; l% K. ^
' }' y! N- `! F' X* t
5.Is Stacked Silicon Interconnect technology reliable?: d4 Y3 h5 Y1 S6 M' G
Yes, in general, internal stress of Stacked Silicon Interconnect technology package architecture is lower than the equivalent size of monolithic flip-chip BGA package since the thin silicon interposer effectively decouples any internal stress build up. Therefore, thermo-mechanical performance improves by reducing maximum plastic strain in the package.
; I; |7 ]( R! T" w9 ?- F
8 b% Q; i6 G4 \& j% w( z+ P6.Who is expected to use the FPGAs made with the Stacked Silicon Interconnect technology?0 R8 y/ w" l, B) T
Customers in Communications, Medical, Test and Measurement, Aerospace and Defense, High Performance Computing, and ASIC prototyping (emulation) who are looking to implement their next-generation, most demanding applications with FPGAs are likely to benefit from the earlier availability of the most resource-rich FPGA devices. By not having to drive off-chip through I/Os (parallel or serial), across PCB traces to adjacent FPGAs, designers that have previously used multiple FPGAs in their system will appreciate the high-bandwidth, low-latency, power-efficient interconnect between the FPGA die. |
|