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LOAD SDC FILE時; |+ B( R6 q1 a; `
Astro 訊息( S$ I; A/ Q! e6 l* L
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2 d% Y, v# P2 Q5 h1 L2 a) A) [Info: starting Tcl processing3 b5 ?6 B6 B. N' ?+ b
Info: building design object name tables
4 V4 E% s% L- `5 a) F, u$ VWarning: No pins matched 'TOP/test/mul/A[26]' (SEL-004)5 }% `1 ?" R' O9 [4 K
Warning: No pins matched 'TOP/test/mul/A[25]' (SEL-004)
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# b& `1 F h' LSDC FILE& R0 D5 }9 [1 b5 W* [& g
* q4 O& Y+ c- f! E2 _# j' {set_multicycle_path 9 -through [list [get_pins \
z) x1 ^, K- L: p5 L+ K; M: d3 @- j G{TOP/test/mul/A[26]}] [get_pins \ D% C5 F5 x/ b3 i( F
{TOP/test/mul/A[25]}] [get_pins \
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Verilog File7 y/ w5 @0 w- @) Q/ D
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uniquify_mul_0 mul ( .A(icwAeYfSum[26:0]), .B(
+ I# u1 Z% h) C+ n7 c icwAeYfNum[18:0]), .C(ae_avg) ); |
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