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0. Check circuit topology and connectivity.# i) Z! a( d: s4 L G& j; {
This item is the same as item 0 in the DC analysis.5 a, l/ ^9 I1 H# A4 X
% I* i ~% P" V8 z1. Set RELTOL=.01 in the .OPTIONS statement.
. G" N5 b6 }$ \0 a+ xExample: .OPTIONS RELTOL=.01! A3 {. {) a( F- y, h( F6 A G" y
. Q+ u- x0 x z9 e' q# R5 m4 W2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.
$ M- P+ b$ {0 |3 _& s$ AExample: . OPTION ABSTOL=1N VNTOL=1M+ p3 a: E, q" n0 j6 D
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3. Set ITL4=500 in the .OPTIONS statement.
, k" ?) O5 u; jExample: .OPTIONS ITL4=500; I( q- ] d6 o1 K4 k2 |* I1 Y/ o% q
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4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance.. H, {5 O3 l0 |. a/ q) d2 i, L
$ j8 Y9 w0 X% B/ x* c6 k# y5. Reduce the rise/fall times of the PULSE sources.) m& a! r" z2 k0 `0 C# |% P, @2 T
Example: VCC 1 0 PULSE 0 1 0 0 0
- A* B6 S; c; f6 I* Bbecomes VCC 1 0 PULSE 0 1 0 1U 1U$ y7 S) N) j' k5 K, g6 e, a3 z% g
( v. _( R& \3 i0 q, D5 O7 F6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources.
& E+ h( x; g3 {Example: .OPTIONS RAMPTIME=10NS5 X: U, @: V7 D) V9 \9 Z' W
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7. Add UIC (Use Initial Conditions) to the .TRAN line.
$ S# ?8 S8 e5 OExample: .TRAN .1N 100N UIC4 S5 q, v8 n: o+ m5 O5 M
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8. Change the integration method to Gear (See also Special Cases below).( k: I. p. p7 k2 v
Example: .OPTIONS METHOD=GEAR |
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