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我目前在設計一個pipeline的電路,且有防bubble機制,但在設計的過程中有些問題~# p' l: S6 O' q# |8 n6 }
想請問一下大家!!/ W3 | h: g* A
該怎麼設計?
5 q$ P; V9 c% F5 }. a% Q2 f以下是我需要的功能~9 D' [2 c$ Z9 ?
| | | | | | | | | | | | | | | | | | | The next stage data full signal | | | | | | | | | DUT full signal to preceding stage | $ m$ a% A m# C; ] R8 v9 i# `
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1 i, U6 z9 u2 Y3 @Thereare 5 pipe stages in our pipelining design. . R1 s% N7 S5 s& B" |( e; G. [
It means that the input data can beobserved at the output port after 5 clock cycles. 6 W2 F7 A9 s! |' j
All the stages must be readyto proceed at the same time. ; X- A6 L( N' Y/ W8 }
When d_full is active, you have to keep the outputdata until d_full is disabled.
9 w8 D1 A* m3 J8 R! ]If d_full is active and all the pipe stages arebusy, you have to generate pp_full to inform the preceding stages to hold data. / J6 `# n+ A' D8 ^6 b6 }
The pipeline bubbles haveto be eliminated when d_full is active.7 R- l; A- N6 ]! v
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