Month4 ?6 d1 h1 M) x/ q& x: `; b0 U
| Topic
. ]0 k" g8 \0 c |
January/ y/ C1 n$ e% B z) f4 j" b9 }
| • Parasitics & Parasitic Extraction/ b9 d! T# z Z* O3 d
|
February
" @* W `2 v1 A3 V5 g! ] | • Verification Methodologies & Tools
7 Q0 H x7 r6 R/ w+ X% _- _6 j• CAE/CAD Tools for FPGAs
7 w8 N6 T% k2 {4 Z$ v( T1 ^( _ |
March! `: y* G) p5 F' n( @* t2 _( E3 g9 _
| • Configurable & Reconfigurable Processors, c4 l0 A# v4 V
|
April
& I+ R9 e+ \5 c7 O5 M* D | • Hardware/Software Co-Design
$ O! S' @2 y' b1 f• On-chip Interconnect, Network on chip (NoC) 4 s6 y3 ~( c' }( y, ?$ D2 D
|
May, ~% b. u4 E1 n+ a; `& P* D0 M
| • Electronic System Level Design (ESL)7 j8 t: g& \' b
|
June
8 m% B# F* d/ Y6 B | • Timing Analysis, Closure, & Sign-off+ k- S. I- h* N1 h F3 z
• Low-power Design Methodologies & Tools4 [4 \* i5 T& J- E8 k" }# `
|
July) ^0 w2 I1 G- B7 x- W) j
| • FPGAs in DSP Applications
3 H! J! p4 `' d# |8 Z |
August
* ^( V2 d2 \' G | • Formal Verification Methodologies & Tools
9 u, u4 v# _4 q" c9 o |
September
; X( u, T0 o, B# C+ j7 I | • Structured ASICs & FPGA-to-ASIC Conversion; o9 k2 T( }# ]
• Design-for Manufacturing/Yield (DFM & DFY)
$ I5 a# x9 D8 g% S2 n+ I; X- L5 p |
October& a a0 w, Z' Y
| • ATPG, BIST & DFT- C5 n1 ?% a. a* a( V o! ?" r
|
November
5 O- K I: p1 K1 H4 O9 v | • Physical Design (Partitioning, Floorplanning & Placement, Routing, Optimization)
/ U# o" M* @$ R8 K0 r7 f• Device/Circuit Modeling & Simulation
- A4 u- I2 t- {9 O |
December
7 Y( R, B9 ^0 e( z: J! X! P% d" r | • Analog & Mixed-Signal Design( f# j/ O6 M' v |
|