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AMD Geode LX 800@0.9W處理器
General Features: S+ a2 z0 j2 E& X$ x
■ Functional blocks include:4 ?5 ?" r( {$ K8 Q# h4 I B
— CPU Core
h8 |! q7 p/ b1 D Z" n— GeodeLink™ Control Processor4 e7 u _% |2 \$ _, ^
— GeodeLink Interface Units: a# I* d' m% L* c
— GeodeLink Memory Controller
$ _. H& ?; g8 r+ T" V; {) Q* s- [— Graphics Processor
; y- w6 Q4 _# P+ N7 w. z# L% Z: `— Display Controller; I/ |1 N4 q0 @3 o; z) L. d
— Video Processor
2 e5 P5 G6 m [9 _ C– TFT Controller/Video Output Port
0 _! I# E7 k- R( Q: ?9 i+ b2 B5 N— Video Input Port
; W. W" d3 x' a$ i! e— GeodeLink PCI Bridge: N2 J9 a. c; k4 B
— Security Block
6 K' L+ t( H7 Y■ 0.13 micron process
2 U+ Q& ]$ p3 U2 r7 q" H■ Packaging:5 S% ]% Q3 \! r# A5 z1 ~2 \6 @9 B
— 481-Terminal BGU (Ball Grid Array Cavity Up) with
3 S% P6 q; F" I6 |internal heatspreader0 M* q1 e/ `- j o- ?
■ Single packaging option supports all features6 p3 y/ j% d9 T" E3 m8 g, }/ x
CPU Processor Features# r. M( N2 i) D0 S3 L
■ x86/x87-compatible CPU core9 f3 R$ W7 H% [; O# U" ^& E- ~
■ Performance:$ Q5 A+ }- Q8 ~! X" g' R6 o
— Processor frequency: up to 500 MHz
; D7 b, X- V2 ]— Dhrystone 2.1 MIPs: 150 to 450
7 ]' r) c! I# N3 I ^* _' f: i— Fully pipelined FPU9 n4 y& ]1 P9 j& ?5 t" a/ m
■ Split I/D cache/TLB (Translation Look-aside Buffer): |" o, g5 ^! Z1 o; L: Z
— 64 KB I-cache/64 KB D-cache8 O) _' q9 W* N7 B2 n- m
— 128 KB L2 cache configurable as I-cache, D-cache,
( O" i* R4 k7 W1 P* }5 c5 u4 N& ior both$ g4 e' p: O* M0 O3 o, e: g
■ Efficient prefetch and branch prediction
4 t0 _1 \$ k7 b! ~3 T' F■ Integrated FPU that supports the MMX® and+ o; {8 A) } Z- C- n( P4 B/ ~* w9 b
AMD 3DNow!™ instruction sets) u0 ]3 g6 `7 q( i; |# c3 [
■ Fully pipelined single precision FPU hardware with% {1 w$ L u+ {/ F' b9 k" t1 |7 V" m
microcode support for higher precisions3 e* J% E- x0 k9 r0 G
GeodeLink™ Control Processor
+ V; D' W' e% k: }$ p■ JTAG interface:5 }7 x6 |" c* p% m5 s5 c) ^7 q
— ATPG, Full Scan, BIST on all arrays u* U: L! L3 ?% k% u' ]. _
— 1149.1 Boundary Scan compliant5 Q" b$ n( ?% z, P' q* L
■ ICE (in-circuit emulator) interface9 J, U* n# A8 N- b
■ Reset and clock control
) u+ S I& X& x! @' ]( i0 v■ Designed for improved software debug methods and& T+ G1 l8 [4 L0 F( n* d1 `, e
performance analysis
" U6 b: M: f% p2 D■ Power Management:
- x2 W) q' l5 L. K# [5 g8 ]— Total Dissipated Power (TDP) 3.8W, 1.6W typical @
4 E- v3 W S! }% O2 b500 MHz max power
0 Z7 N4 I' i2 h7 |: e- m1 J— GeodeLink active hardware power management$ z+ M; F0 B$ I
— Hardware support for standard ACPI software power
" f* d3 Q1 t1 S# l8 |5 Q! N* umanagement- \% O7 j6 X( F* }0 u
— I/O companion SUSP/SUSPA power controls
! f* a+ e" o: A— Lower power I/O
# S, v$ M5 s4 p! r [5 c7 Q2 K' h2 m— Wakeup on SMI/INTR
% B- g0 u6 l* a, ^4 S; W5 }■ Designed to work in conjunction with the7 u4 f( R, O6 E, B, b& z
AMD Geode™ CS5536 companion device
4 `9 I2 b& S8 ^GeodeLink™ Architecture, y$ D1 H. o ^( z
■ High bandwidth packetized uni-directional bus for
3 F s- y6 u( |! _" linternal peripherals9 p8 j0 `& O, G- I& u6 a8 p
■ Standardized protocol to allow variants of products to be2 h% V' n6 ]. w% O G; w6 x
developed by adding or removing modules
* m: p4 o( S h0 [3 M# [■ GeodeLink Control Processor (GLCP) for diagnostics
! `# Q- t6 C) D* w! A$ n0 hand scan control; u0 k! J, h, T* p, B- R
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
1 s- J2 T7 y+ U" Z8 U: w6 qGeodeLink™ Memory Controller+ Z& I* _; E- R0 u1 _8 C8 t
■ Integrated memory controller for low latency to CPU and
; S' c: j* x& ]( y+ R$ Y2 mon-chip peripherals: N/ _, u0 N# t+ `
■ 64-bit wide DDR SDRAM bus operating frequency:
8 s3 h5 S A. X1 n1 E @— 200 MHz, 400 MT/S5 z+ b* S( {- ^
■ Supports unbuffered DDR DIMMS using up to 1 GB
/ Q, v5 {, o; V) Y5 e- u) o( tDRAM technology* e" d) L1 |- U* r/ j( P
■ Supports up to 2 DIMMS (16 devices max)
$ C0 A- |) \) Z- v2D Graphics Processor7 b3 u0 e: @, ^6 [$ h3 \
■ High performance 2D graphics controller
2 w# @" F+ }3 D0 c# Q$ j5 L- q5 K2 s1 u■ Alpha BLT
* O: o' t% }0 q# s, a1 O# o■ Microsoft® Windows® GDI GUI acceleration:2 Q$ Y5 M" h4 Q8 V9 z0 B% l& Z
— Hardware support for all Microsoft RDP codes( H7 C3 W9 Q2 n* [1 j
■ Command buffer interface for asynchronous BLTs
) L( j! g8 K. L■ Second pattern channel support
Y5 t* y, v* W9 c6 n■ Hardware screen rotation |
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