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一般dly'event and dly='1'是不能寫在case裡面嗎?
7 T" d! Z* |/ P( p: X因編譯會出現以下訊息
+ j( g0 R* v, l/ G5 k3 d& XError (10822): HDL error at CUB.vhd(70): couldn't implement registers for assignments on this clock edge
$ d( n3 f/ ~4 C0 ?4 y* f' @2 PError: Can't elaborate top-level user hierarchy
1 s5 Z D* i: @1 j/ nError: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 15 warnings0 @* R5 b+ p( `* Q2 g
Info: Allocated 144 megabytes of memory during processing
1 F4 i6 a0 \9 q+ I) z9 T; E Error: Processing ended: Fri Oct 18 21:24:23 20131 M% |/ W# ^1 A) r
Error: Elapsed time: 00:00:025 N! ]9 O5 X1 g" v4 L
Error: Quartus II Full Compilation was unsuccessful. 2 errors, 15 warnings- O: Q7 w, k+ `' B, L1 N
2 O5 y, r* P/ i# Z8 x程序如果寫的不好,可以幫我改寫,因是自學,所以比較少機會可以看到其它人的寫法!6 m" v2 `" f9 s7 T" M% ^: k
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Library ieee;- P: p7 h& T' H4 X' j' d
Use ieee.std_logic_1164.all;8 L+ u: y- m7 m- I8 d4 T
Use ieee.std_logic_unsigned.all;( p: b1 G* k* `1 R# p4 z
Use ieee.std_logic_arith.all;1 r5 d5 b5 \( s2 H% T5 ]+ h
/ F5 r/ n; ~1 Z; ^; `" O N! y& [Entity CUB is( Q2 e0 y' D6 K+ e3 D* w3 D) s$ c
Port(/ c- r8 B! q+ F! T
sv_ctrl,coll_manu,coll_auto,count_v2,T1I,T2I,dly:in std_logic;
% |- `5 {8 [ w* D* X' f% u. o7 ~5 e' I$ J count_clr,coll_up,coll,cold_pin,T1O,T2O:out std_logic
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end CUB;
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Architecture cub_arc of CUB is
7 z& _. C7 |6 y. e1 Z; a9 Tsignal d : std_logic_vector(2 downto 0);, O& Z- N. R" e
Begin# @" ^' ?+ x0 M1 E3 h
$ n5 t1 M( H, aproce1rocess(coll_manu,coll_auto,count_v2)8 Z& d% d! l0 D0 X
Begin
7 K; G& e7 V. E8 L6 A if coll_auto='0' then
" M" [% I; ^/ n1 Z8 [: |7 ~# X if coll_manu='0' then
1 C4 R1 `# }1 Q1 P R' s if count_v2='1' then
6 _- W# p; C, ^$ V4 b count_clr<='1'; - N1 N8 S8 F8 @4 C/ n# r
else
U* h S; T3 R; B+ @ count_clr<='0';: b/ B" o! @, K. r% G6 C
end if;
, I- a, {/ R# Q% {1 s) o) @5 J7 S$ y coll_up<='0';' i v. [- o( K
coll<='0';
" m/ u7 q$ k: a, I2 P& E cold_pin<='0';5 c! X! K6 `! C2 X4 S
end if;5 [) N. n9 K7 s @
end if;
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/ d: C8 D! U; N. L if coll_auto='0' then
6 X7 S6 J; P$ ~* N6 ^( ~' W if coll_manu='1' then, m W( _, q% C5 @/ Q" f
if count_v2='1' then
9 J- ]* F6 I: m# J1 R5 Y count_clr<='1'; + J' E: z$ I" h3 H# z, S
else) r+ t& z# @$ N/ S- T
count_clr<='0';
* q" I2 F) o. k3 I$ A) C% | end if;
5 Q0 V5 ^" k& S8 U1 ^ coll_up<='1';
x" x. ^) v0 Y4 ] Z* H3 \ coll<='1';# B7 |+ A5 D% l! e
cold_pin<='1';
, r1 [$ [) F) b8 y) M end if;
! L0 T) b; c/ A( I end if;6 F, A2 u% C$ B
& B4 F6 {& i) i0 E if coll_auto='1' then- I$ D/ ]& r, N; G: S
if coll_manu='0' then6 g/ R* M6 Y1 s: N
if (sv_ctrl and count_v2)='1' then
6 m8 z# K, W" `5 _* Q0 } case d is5 z1 U) }* ~2 b/ H( _
when "000"=>
0 e9 r' Q/ j5 `% k4 t* K coll_up<='1';
" ] A O9 w0 I2 @ T1O<='1';4 V1 _' E) ~4 ` I
d<=d+1;
7 _/ d1 b: L. {' h5 |7 m/ i+ J( u when "001"=>
: C! q9 l7 F7 s if T1I='1' then4 x3 x& c& w2 T
T1O<='0';
9 x: J; r3 a f/ s: c coll<='1';* X5 {7 Q: C4 ?- y: F9 T
cold_pin<='1';
9 r" }& D5 X4 t$ |' K T2O<='1';7 H6 ^# p6 m, M+ d! A, u
d<=d+1;
# q- {6 ?0 J$ x: o$ y8 A end if;- q i. ]9 |6 g& D
when "010"=>
0 _8 z9 b& M) O. \1 d4 u8 f# |, @ if T2I='1' then
5 B2 i; ]& W2 ?5 R$ _5 u) J+ R T2O<='0';
5 J# O2 B. b! b7 n- B% b coll_up<='0';
* S' P! \, `) B; x; o7 P `2 ]2 R coll<='0';8 {+ X6 E; ?( A5 S0 g) I
cold_pin<='0';" N' u5 z' o' Y; j
d<=d+1;* U# y& Z0 ]) t: b
end if;9 x% P8 b+ c7 r
when "011"=>
: K1 Y5 x. g) ^6 \$ ~ if (dly'event and dly='1') then" l0 T2 b- m. n4 U2 o9 y& I
d<=d+1;
4 x, o6 @1 P; L: f$ f1 P& K1 T end if;, O, N2 g7 G) |3 j
when "110"=>, V# ]' b. X% P& c9 b% E- ~
count_clr<='1';0 y! a. |$ B7 {% [7 ?2 }
d<=d+1;4 v* _) @! V2 C0 W/ ], N
when "111"=>
5 Z* L& P/ _& l/ e* ] if count_v2='0' then
K% q, S. H) Y! c8 u1 \ count_clr<='0'; S1 ~! L8 g4 _+ Z: c) z! N9 r6 q5 f
d<="000";
" s) ?1 V* X( Y end if;! C8 p# V% h/ A) m9 T& h
when others=>null; u. f. z1 J4 z, _2 [2 h
end case;
6 w1 V: O _( J. c/ S end if;" L* d: D7 x3 Q& J) N' c
end if;# G& q' o4 A3 u. c
end if;
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if coll_auto='1' then- f1 h/ A: U" c
if coll_manu='1' then
/ B: [, c9 O* B coll_up<='0';# l8 p' h% i, G0 O/ ?: m
coll<='0';& S7 q: m! c0 I! ^ Q2 N& K
cold_pin<='0';$ N) [! M$ L4 Y/ F8 w8 j
end if;' Z6 X1 C7 b4 }, f5 W
end if;5 b; ` @+ |" v. S3 `
end process proce1;3 f6 q. K/ d7 }
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end cub_arc; |
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