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0. Check circuit topology and connectivity.3 A+ j, @9 N/ o- ?# \* W- Y
This item is the same as item 0 in the DC analysis.
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3 m, b/ C, s# D' {1. Set RELTOL=.01 in the .OPTIONS statement./ a1 M }$ W/ s7 p+ \
Example: .OPTIONS RELTOL=.01
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0 G1 ~# _! [! @' \2 T/ }2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.1 w1 g5 V4 V4 v
Example: . OPTION ABSTOL=1N VNTOL=1M
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3 s! N9 Q' L2 |1 u3. Set ITL4=500 in the .OPTIONS statement.7 B/ A/ }) c+ j Q" B
Example: .OPTIONS ITL4=500
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, M1 K6 G1 s7 O0 J, R/ |8 T4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance.! u8 X- g7 G) I: Z
7 T# p* R: V! O5 I+ H8 R5. Reduce the rise/fall times of the PULSE sources.
. V# F: ]) m' s; Y+ R$ o* EExample: VCC 1 0 PULSE 0 1 0 0 02 q; m' n$ z' z% X6 d6 B0 y
becomes VCC 1 0 PULSE 0 1 0 1U 1U
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( |+ | W3 i0 `$ U0 |, v2 g6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources.7 E) n7 d! d1 B" p l) a% h
Example: .OPTIONS RAMPTIME=10NS8 w, r! T! J: B% @' K6 Q }: S
: Q+ N T$ [9 @ V7. Add UIC (Use Initial Conditions) to the .TRAN line.7 a. l. D" H/ c4 w! R4 ]5 {
Example: .TRAN .1N 100N UIC
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8. Change the integration method to Gear (See also Special Cases below).% a) R2 t- U( R8 w6 s- a0 _( Y1 a
Example: .OPTIONS METHOD=GEAR |
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