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0. Check circuit topology and connectivity.
6 w4 @; e. f3 m5 p* T5 O& AThis item is the same as item 0 in the DC analysis.
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# z+ Z% Y3 j0 }1 W& z: Q1. Set RELTOL=.01 in the .OPTIONS statement.
, S) i( O7 R H% p3 ^- n. PExample: .OPTIONS RELTOL=.01
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3 t4 O4 |* j' [2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.
, q9 _! D3 O5 @; }4 y/ EExample: . OPTION ABSTOL=1N VNTOL=1M" D) f- _7 ]: P. Y- u t
3 o! ~6 e! b% W- Z+ U. G/ q. ?3. Set ITL4=500 in the .OPTIONS statement.
& Y- k) F- \$ D! mExample: .OPTIONS ITL4=5000 _, ]2 Y* p% p
& F' O, \8 i1 n. W& z4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance., ~9 j2 t! @ w! m8 q+ x+ r
0 z. |6 @; g4 o" N# g: Y2 @5. Reduce the rise/fall times of the PULSE sources.7 f, P' k* v% C; y
Example: VCC 1 0 PULSE 0 1 0 0 0- m! q3 k( }! D9 h
becomes VCC 1 0 PULSE 0 1 0 1U 1U
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6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources.
" M, u1 b. B7 h( I" B$ RExample: .OPTIONS RAMPTIME=10NS
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9 k' ]( V6 |0 x( @0 E- O7. Add UIC (Use Initial Conditions) to the .TRAN line.- W+ W s, H2 C4 j$ q$ I
Example: .TRAN .1N 100N UIC/ L( I% t" k7 y6 J1 ?5 g0 r
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8. Change the integration method to Gear (See also Special Cases below).
6 Y, g2 x$ X! Y" `% k" xExample: .OPTIONS METHOD=GEAR |
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