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Sr. ASIC Design Engineer (encoder/decoder); n3 n6 d* o2 W" {) J9 b# [ u7 H% O3 k
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公 司:a leading developer of advanced digital imaging solution; Y2 m( ^2 \0 s% \% \+ D
工作地点:上海
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Position Overview: The candidate will join a team of highly competent ASIC designers involved in design, verification, and implementation (ASIC) of advanced platform for XX''s future generation multi-media products.
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; |$ Z( s' R, M5 { ~. M主要职责 (70%) 2 R) W! O& J' s2 F9 I5 K" l
In-depth knowledge of TV encoder and decoder design. Good understanding of TV system design. 0 [2 s# k2 g h, p
Proficiency on digital filter algorithms and hardware implementation. ' Z* w2 m$ w8 {/ N) R# i" G
Development and verification of complex IP module, integration of the IP module into the Soc devices, top-level design handling, system level testing. 6 O4 i* C$ q3 t1 X6 | W
Participate in the FPGA platform development and lab debugging + o1 L/ {6 i9 L, A$ D8 B: u
0 V6 ~$ k4 I& w7 W其他职责 (30%) 4 }/ ]9 f( p5 D$ r
Participate in block level architecture design Assisting embedded FW development.+ n T5 Z! T/ T, b
职位要求
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经验/技能 6 T$ a7 n* c0 ^3 z
1. Strong knowledge of TV technologies, knowledge of image signal process and CCTV system is a plus
. O9 `# N% `$ U2 G2. Strong knowledge of ASIC design flow. Can define Micro-architecture of the IP module and /or sub-blocks. And able to write detailed engineering specifications. 9 L, j4 j/ D0 B8 p- W! P2 I% F
3. Good communication skills, especially in technical writing and reporting;
. K" X- Y5 R- n4. Self-motivated and ability to excel in a team environment.
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教育
* u. F, c# a: `& W. v4 W" n, kMSEE/CE with 3+ years of industry experience |
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