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Staff Verification Engineer& R8 l- Y" Y% K' B" h
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公 司:one famous IC company
! o# [& ~7 J" h. Q3 o; n工作地点:上海
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, ~, [. z" f. U, p4 {Qualifications
_' Y" v: O% O0 `MS in EE/CS/ME.
, H M0 B' t. w/ J5 kMinimum of five years experience.
* G3 ^' u( K* o; ~( I# {& w+ rAdditional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.9 J/ {/ }& `- e
Candidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
7 Z, m& @( ?6 r& [6 ^! h$ z$ F- UCandidate should be familiar with industry standard ASIC design and verification tools and flow. 6 l# p; o. k8 \2 D% J; L& ^
Good knowledge ddr protocol and computer system achitecture would be an added advantage. 5 w: V: P8 c. Q+ i
Good knowledge of Perl and shell programming would be an added advantage.
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( v! y4 g; T/ w, |* xResponsibilities: 5 u" z* a: u$ T& E3 X
-Understanding the expected functionality of designs.
) D7 c/ e; J/ ?, i+ K( X1 M9 \-Developing testing and regression plans.
5 q7 q, a6 r2 {-Designing and developing verification environment.
% f! g' O2 x9 r-Running RTL and gate-level simulations/regression. : M2 J; a( g0 O/ Q& B) Z- g
-Code/functional coverage development, analysis and closure.
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Requirements:
7 q3 w9 ]4 u/ E% o pExperience & Skill: 5 Years & t) s5 E$ d/ W: c$ ~0 o" i& H& V5 i
-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
3 o& q' C& B: i2 a6 n9 N8 b-Knowledge in ASIC/FPGA design process and verification tools.
2 O# ?, F# O, C" |' E8 \0 A-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
3 i7 n) F5 G/ m* F4 i, V, t2 Q# q- Scripting and automation skills (tcl, perl, makefile etc) a plus. 6 L' g4 Y( L5 g( ?* Q9 h! n
-Familiar with C/C++.
7 o) Y$ t' U7 W5 t-Knowledge of DDR protocol a plus. - S, I1 f& [% |- A( Q! U, y2 h# a
-Independent and self-managing. |
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