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//some example
9 A3 v8 c+ j$ d$ o& W% x
8 I; `( L6 g0 ~+ Z" o0 l// define variable
$ C% N4 T+ n8 S5 O3 U) x7 h! O: d& yVARIABLE RVM1 0.077 // Metal-1 resistor & y( b V1 D# N& Q: C x6 S( X
VARIABLE RVM2 0.055 // Metal-2 resistor
% u5 N; V, T$ Q* V0 {% ^& D0 yVARIABLE RVM3 0.055 // Metal-3 resistor5 R1 d" K3 M1 F3 C* s1 s2 C
$ R. x* V* N% }+ s- B7 [// lvs option4 N0 Q5 R* X) J. n, p( a
LVS SPICE PREFER PINS YES! L) N) ?5 c2 S( @3 `3 f6 u
LVS ABORT ON SUPPLY ERROR NO
& l# m' G) F5 |" v+ C$ u" vLVS ALL CAPACITOR PINS SWAPPABLE YES' n: v0 ^+ u( o8 W1 q% O/ w3 L: ^
LVS RECOGNIZE GATES NONE' I v+ ?! h/ d# {& }
LVS IGNORE PORTS NO6 u9 I' @( z- M7 z1 z' C
LVS CHECK PORT NAMES YES4 b* C2 p' I2 E2 b! L9 ?( b1 l( W5 w* C: g
LVS REDUCE PARALLEL BIPOLAR YES
8 `" _1 D4 H0 m9 L cLVS REDUCE PARALLEL MOS YES" I' x8 @9 V; T$ ~# y. f! ]
LVS REDUCE PARALLEL DIODES YES
* D" I Y" i4 PLVS REDUCE PARALLEL CAPACITORS YES
9 I3 j" V/ i3 DLVS REDUCE PARALLEL RESISTORS YES
/ P- ^3 \6 m6 m! n$ OLVS REDUCE SERIES RESISTORS YES //Smashes series resistors% b! `5 M8 J/ }
LVS REDUCE SERIES CAPACITORS YES //Smashes series capacitors
7 U$ r# g H. E8 D* v+ i7 `6 mLVS REDUCE SPLIT GATES NO //Smashes MOS split-gates.2 e9 t/ C! M5 G6 X: K8 n+ ~
//LVS FILTER UNUSED OPTION B D E O7 t: Z# B% j+ [; e
LVS FILTER UNUSED OPTION AB RC RE RG
' F8 [* f6 H& S3 s! x/ gLVS PROPERTY RESOLUTION MAXIMUM 65536 // ALL( `- X$ e' U2 a! |6 t
) `9 V, `5 F3 V: `2 p0 `
// layer definition( K, P" x! w$ b4 Y& O3 [
LAYER DNW 1 // DNW -- Deep N-Well
3 U- x4 J4 F# H9 {LAYER NTN 11 // Native Device Blocked Implant
i" S8 O1 |8 vLAYER NWELL 3 // NW -- N-Well
, E5 x) I5 e1 H. z5 A* q& oLAYER OD 8 6 7 // OD -- Thin Oxide4 N5 M( I2 y& D4 b& S
' p6 l q/ J( _$ \
// layer operation- V9 j( c3 g' E
rpolywo1 = POLYG AND RHDMY
2 ~# a" r5 A6 c" |- c- v2 J2 @rpolywo2 = rpolywo1 AND RPO
% M1 p0 S) d" \. B. n- z9 ddiff = OD NOT RODMY
( Y8 L. M* d# O% S' frp1 = RPDMY NOT INTERACT diff ' \$ y6 @" S' m0 u" i" L
p1rdum = rp1 INTERACT POLYG
, P4 ^4 g. _- x# y8 N( O% D9 n
9 \4 W, Y1 s: K/ d8 o6 t$ x// connect statement; s8 m! ]$ K8 M* F; \; k
CONNECT metal1 c2poly BY pl2co
! r c. d, d: j. G; W* h+ d6 o: W/ mCONNECT metal1 tndiff BY pl1co
. _4 K: G' ]7 P( l& q+ ^! WCONNECT metal1 poly BY pl1co/ R9 a( {9 H0 ?% ?4 O
CONNECT metal1 tpdiff BY pl1co) Z1 O. d+ x% }9 V+ S2 ~* K4 K; ]9 x# c* |# a
CONNECT metal2 metal1 BY VIA1
& z3 H1 e0 ]$ [4 I/ s2 ZCONNECT metal3 metal2 BY VIA2
! W* I. y7 T ~CONNECT metal4 metal3 BY VIA3/ y( V8 m" [7 |. [( n7 \6 `
CONNECT metal5 metal4 BY VIA4; Q" B, _; }* f( |9 ^ r
CONNECT metal6 metal5 BY VIA5
7 D) |- V0 c$ d- K5 v: M6 D# PCONNECT metal7 metal6 BY VIA6
4 A) ~5 ^7 N4 w- n6 y! }CONNECT metal8 metal7 BY VIA74 c8 f( Z$ V' `9 l8 |; G
CONNECT metal8 CTM_M7 BY CV7" L% X) b( \1 u! {/ A
$ m5 h9 ^! N7 m: `6 N// device definition; _ o$ L {- V0 X/ k3 v
DEVICE MN(nmos) nmos poly(G) ndiff(S) ndiff(D) psub(B) [9 ]( ^" }$ L4 m; z2 ~( n, L" W M
property W,L/ v! s }1 H# s% V7 V# k
W=(perimeter_coincide(nmos, ndiff ) + perimeter_inside(nmos, ndiff)) / 28 H6 S. d% G( Y" t* \! k8 A# O, g
L=area(nmos) / W- a4 k) R0 f% K( X$ S% H. ?+ }
]: Z0 c/ | l1 y1 Z5 a
& D; N: t2 D/ c" P6 Q) l// trace property8 k2 S/ X2 n7 @1 h9 }" O
TRACE PROPERTY MN(nmos) L L 02 ~' y, L( s4 E
TRACE PROPERTY MN(nmos) W W 0 |
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