ASIC設計工程師如何保住飯碗？

innoing123

Junior Physical Design Engineer
公      司：A famous IC company
* t. e6 @- ^, w$ T7 e工作地点：北京
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Position Tasks, Duties and Responsibilities
7 r  ^- I  D$ }  f+ V' x7 G3 \The ASIC Physical Design Engineer will:
        Complete third party IP integration and ensure vendor guidelines are followed.
        Responsible for physical verification (DRC/LVS).
0 t/ W- w; w3 ^; Q2 W) S- R        IO ring design, fullchip floorplan.
        Block level implementation.
$ K0 H2 h/ B3 A0 E        Work with front-end engineers to resolve problems and achieve design closure.
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; T7 _3 h4 B, ^) p$ MCandidate Qualifications:
' Y2 I+ z- E, V8 }1 n  t0 NCandidate must:
        Hold BSEE (MS preferred).
! }1 J7 z: b! Y, s+ s# C8 h2 z; s6 j        Have minimum of 3 years hands-on experience in full flow IC back-end physical design and verification
: p7 P5 z5 g$ k        Be able to complete block and chip level tapeout quality LVS and  LVS and DRC.
* [+ A1 ]6 ]2 v$ U& w        Have the ability to independently identify and resolve design, tool, and flow problems.
3 \8 `( H  i5 b% }' w        Have related timing and physical concept.
3 _0 @0 C' C- [1 A$ d        Be able to design and implement physical design strategies and methodologies for deep submicron designs.
        Familiar with EDA tools.
        Familiar with Linux environments.  

Any of the following is beneficial:
. B& v% h" v9 ]6 C- R        STA constraint design
5 d2 U8 X1 M/ a- N9 h       Equivalence checking ?RTL to gates, and gates to gates.