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Senior ASIC engineer
客户 a start up company with innovative technology2 B5 h9 f3 @, p
地点 Shanghai m& ^3 Q8 {7 P4 R5 s
8 @) Y& e Y/ W% @. h% U
职位要求
& c I: [1 {( ]4 C* G) ]1 ?4 X! Z5 + years experience in ASIC design -> must
) \$ W4 A) S4 |# V· MS in Electrical Engineering (or equivalent) is a must have
- D) i9 A, {+ Q8 Q/ t· Experience with WIFI baseband/MAC or related wireless baseband technology desired -> plus
/ d) J' c r" S· System on Chip (SOC) Integration Experience, including AHB/AXI, CPU integration -> plus8 `8 G0 Z$ x9 J' d4 U9 L: S5 y
· Experience with interfaces such as SPI, SDIO, USB -> plus! G! l0 f' t1 I/ U9 b' y
· Working knowledge of networking protocols such as TCP/IP, 802.3, 802.11 -> plus
* h6 E- k H. [" b1 l· Must be expert in Verilog RTL language -> must
, b5 K O& e- [2 O1 Z· Must be familiar with the ASIC design flow from RTL through synthesis, including the tool flow. -> must# Q) W8 j9 h$ ^
· Verification experience – Verilog, System-Verilog, Coverage Analysis -> must for verification engineer, plus for design engineer
7 m' I. ]4 M7 F! U4 f" Y# h5 v# @· FPGA emulation experience -> plus) D; Y, H& @" d$ i1 {0 C8 V* v
· Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging -> plus
7 A) T+ @4 J, R r' W( v, t· Experience with digital backend |
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