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[經驗交流] ASIC設計工程師如何保住飯碗?

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1#
發表於 2013-4-24 13:55:31 | 顯示全部樓層

Senior ASIC engineer

客户 a start up company with innovative technology2 B5 h9 f3 @, p
地点 Shanghai  m& ^3 Q8 {7 P4 R5 s
8 @) Y& e  Y/ W% @. h% U
职位要求
& c  I: [1 {( ]4 C* G) ]1 ?4 X! Z5 + years experience in ASIC design -> must
) \$ W4 A) S4 |# V· MS in Electrical Engineering (or equivalent) is a must have
- D) i9 A, {+ Q8 Q/ t· Experience with WIFI baseband/MAC or related wireless baseband technology desired -> plus
/ d) J' c  r" S· System on Chip (SOC) Integration Experience, including AHB/AXI, CPU integration -> plus8 `8 G0 Z$ x9 J' d4 U9 L: S5 y
· Experience with interfaces such as SPI, SDIO, USB -> plus! G! l0 f' t1 I/ U9 b' y
· Working knowledge of networking protocols such as TCP/IP, 802.3, 802.11 -> plus
* h6 E- k  H. [" b1 l· Must be expert in Verilog RTL language -> must
, b5 K  O& e- [2 O1 Z· Must be familiar with the ASIC design flow from RTL through synthesis, including the tool flow. -> must# Q) W8 j9 h$ ^
· Verification experience – Verilog, System-Verilog, Coverage Analysis -> must for verification engineer, plus for design engineer
7 m' I. ]4 M7 F! U4 f" Y# h5 v# @· FPGA emulation experience -> plus) D; Y, H& @" d$ i1 {0 C8 V* v
· Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging -> plus
7 A) T+ @4 J, R  r' W( v, t· Experience with digital backend
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2#
發表於 2013-10-16 14:21:03 | 顯示全部樓層
资深变频空调方案研发工程师5 ]8 i3 Q+ G1 ^0 l$ X- m* t
8 g  C( D$ X' O$ G
公      司:A famous IC design company in shanghai
; D2 H$ t! X) J) F; X工作地点:上海
* |: o$ D$ c' `+ B3 R* y' R
7 ^/ U" c: V: u" C职位描述5 G" T% M+ L& i
從事變頻空調控制軟件的研發。
1 q" T- s0 Y/ p8 w, G
3 ~4 m2 r# M* f) K职位要求
: S% {' M9 N& M3 `& |. f; Z, X. n有變頻空調控制軟件的研發經驗,熟悉變頻空調控制算法及相關技術
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3#
發表於 2014-1-15 09:44:14 | 顯示全部樓層
数字芯片设计工程师(DFT/综合)" |% F8 [# G  A# l! X: e
公      司:A mobile chipset semiconductor company, l5 f" ]. _; W& Y7 j8 p
工作地点:上海
/ c, |0 b! _4 |/ q( o8 W$ a9 b+ p4 L" ]7 s4 F- _! I
职位描述: . M, W& \1 s: {" b/ k9 F
1、To provide and support SYN&DFT work for several projects in parallel  2 z9 I. Z0 S2 G9 l) Q% P5 N
2、Run block level implementation for each project, include synthesis, DFT and LEC
3 c$ x2 @2 B9 G( q( L3、Support block level physical evaluation  ( l" x, d5 w5 D% l
4、co-work with designer and provide block level SDC file ' l  A6 N. K. }6 r. j
5、co-work with Back-end team for timing signoff5 G/ W7 B0 _3 @9 u: b& Q2 x  A# x
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职位需求: 0 i9 |+ C! @) x- f; |- l
1. 了解集成电路设计的基本流程 ' S2 R2 f8 Z+ s$ ^
2. 相关Synthesis, formal check 和DFT的工作经验。(3A, 3B, 3C精通一项即可)
9 p, \5 H. L3 z7 z* V( X. C3A. 有超过2~3个项目的synthesis 经验, 用过RTL compiler且熟悉timing的相关知识  
! C- c" X: Z* g& l6 d. R# o8 ^3B. 有超过2~3个项目的formal check经验,熟悉CPF的low power flow
5 m, V- D3 i  G. M2 ^! w4 ?3C. 有超过2~3个项目的DFT insertion经验, 用过Mentor DFT的优先考虑 9 D8 @' ~+ [( r
3. 具有良好的英语阅读和书写能力。
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