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RFIC工程師門檻?要當RFIC Designer的三大條件?

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1#
發表於 2013-12-26 10:14:11 | 顯示全部樓層
Field Applications Engineer9 Y; d  W' C/ G3 E9 E& O
公      司:A famous IC company
8 m8 T/ `- l& e4 a3 g7 Z工作地点:深圳4 H+ }) f4 X! _

$ H7 \6 w# k( DJob Description
- }8 I' S# ?9 d* j: ^$ HLead and manage a team of talented FAEs in supporting customer projects.  2 t# j+ Q. t. Q6 e, H7 @4 b$ L
Design or modify PCB reference design to implement preferred RF & BB IC layouts.  6 n9 [( M4 _+ R5 P0 n
Work with engineering to implement hardware QA procedures to satisfactorily test hardware releases in advance of shipment to customers. & j1 l; L/ r7 y5 t
Debug customer hardware/firmware issues and track the changes through engineering. Document appropriate ECN’s within engineering or outside engineering services companies. 6 f: n% q2 U7 y2 W" n
Write appropriate documentation to support ***’s development kits and reference designs. Create HW related customer support documents, application notes, and FAQs.
: n; I& E+ s6 a  `Work with Engineering to implement hardware release standards and track hardware revision history among customers who have XX development kits and reference designs. : l' K" u% y' }
Work with the Sales and Marketing Teams to promote the company’s products and technology advantages. * e, [# O* q8 q0 Y% p3 g
Work with the Sales and Marketing Teams to qualify the technical feasibility of new potential programs.  
# m; M) G+ C) m5 \Work with customers to bring programs from concept stage through to production.  
& u- [6 L5 w  H* Z' cWork with customers and the internal Quality team to identify, debug and troubleshoot product quality issues.* ~6 L7 Z! A! |3 X2 N
) O: N7 v' F& j$ `! q. G
Required Experience  / T% ^2 V1 r0 K. i& Y- V8 o
BS or MS in Electronics Engineering.  & p: i4 u- @3 F. _; @2 H, t
Minimum of 10 years of hardware development and a minimum of 5 years experience in hardware semiconductor applications engineering % t7 r7 `, x% K& b) V, T3 [( N4 s
This individual must have experience working with customers in the early phases of development, and in particular, experience in defining Development Kits and reference designs is essential.
( L& q' h1 K# [6 t# I2 c0 P- `9 RThis individual must have experience working with customers in the early phases of development, and in particular, experience in defining Development Kits and reference designs is essential. 5 Z6 \$ x" p& d; N2 z  ?
Experience with communication IC’s, networking and video products are essential. Skills include hardware design, hardware support, IC debug, RF layout, development kit, and reference design support.   Q0 b5 R& X. a; @6 i" ]. N, d! f
This individual should be familiar with test equipment, schematic capture, and PCB layout tools, and production layout issues for mixed signal and RF systems. & q; C4 L3 w% Z( `% w( S+ I7 ~
Decent English communication skills in both oral and written.
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2#
發表於 2013-12-26 10:15:05 | 顯示全部樓層
Sr Analog Designer8 p, d) J! ^! _2 m5 L" e9 F
公      司:A leader in high performance analog and mixed-signal IC design+ b/ Y- ^2 ^9 H! d
工作地点:北京
" A+ d7 i& W) g4 P6 j5 ]9 A4 ?' K- j- d( J8 P
Education and experience requirement # G* Y! m/ q# [6 H; h
o     PhD in EE, MSEE and 5+ years of and/or mixed-signal IC industry design experience; or BS and 6+  years of analog and/or mixed-signal IC industry design experience * N/ E5 G; k  ~+ Q% Y: o
o     Hands-on CMOS product design experience in two or more of the following areas & K* @, s# @, k: r
o       Receiver front end, including analog front-end, demodulation, channel selection etc.
8 U) P3 Z- E/ X0 t$ zo       High-precision ADC, including sigma-delta, pipeline etc
8 @- x) a$ ^" }  f8 p+ z* ao       High-precision DAC % P$ B1 p5 X4 V
o       Fully-differential continuous and discrete-time (e.g. switched capacitor) amplifier/filter design ! |8 U* n0 j2 C
o       High-precision oscillator/PLL/DLL # a1 ]0 S* T& S; N
o       Low noise voltage reference ; A: o5 S8 a: v* z% I  X8 X; N
o       On-chip high-voltage charge pump , n% E1 j3 u- j8 W' g; C
?      Experience in system level definition, modeling and verification a plus
' e1 b" e8 j7 M9 C- ]* A& Z$ N) s' ??      Hands-on experience supervising layout and post-layout verification : ?+ J( {) d& d0 p
?      Proficiency in tools + H8 x0 o- u) @% h: E
o       Cadence design environment 0 C# V; T5 J/ X4 \# |/ e
o       Verilog/VerilogA/Matlab or other tools for system level modeling and verification  a plus
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3#
發表於 2013-12-26 10:15:56 | 顯示全部樓層
Sr Analog Designer* T, w& ]9 b# }5 l- v, \. i
公      司:A leader in high performance analog and mixed-signal IC design
/ G' B( J: G' X% Z工作地点:北京
& w9 y2 y7 F3 L9 C7 p8 p% _. u9 N/ T4 _+ {
Education and experience requirement
1 w9 R; n: y# k" K1 A- l      PhD in EE, MSEE and 5+ years of and/or mixed-signal IC industry design experience; or BS and 6+  years of analog and/or mixed-signal IC industry design experience
- t0 Z8 x. A# t% D5 W      Hands-on CMOS product design experience in two or more of the following areas
& s- i" i6 i. \       Receiver front end, including analog front-end, demodulation, channel selection etc.
6 u  L6 y1 S& M+ \7 n       High-precision ADC, including sigma-delta, pipeline etc ! J: A: O' ?2 G5 \2 B; L# \2 E6 }+ Q
       High-precision DAC
5 u, ~6 Y4 x. o1 [8 G4 g       Fully-differential continuous and discrete-time (e.g. switched capacitor) amplifier/filter design
! N7 Y( ?( o# [2 x. n8 _       High-precision oscillator/PLL/DLL
1 {3 ^0 E8 I5 B: J- a       Low noise voltage reference   H! v. z1 s: k; H% T7 o
       On-chip high-voltage charge pump
0 U' Z, j. F3 `+ p  z      Experience in system level definition, modeling and verification a plus
6 {4 v2 j# q% u* V, _4 y( c      Hands-on experience supervising layout and post-layout verification
- @; `+ p4 r+ r. W      Proficiency in tools # a, z$ h2 L# L5 o3 n
       Cadence design environment
1 \! n+ y7 \' E) N3 g       Verilog/VerilogA/Matlab or other tools for system level modeling and verification  a plus
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