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Staff Verification Engineer: c% R$ R5 |/ H
6 l7 \ c1 |: U/ e( e公 司:one famous IC company
& s& F9 L6 [3 ^: P# i" x$ t, j工作地点:上海2 T6 a+ |/ @* v6 {" t# A
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Qualifications ) T9 w6 m1 W7 j6 V$ ~
MS in EE/CS/ME. , e2 i- C. R* [, }. V
Minimum of five years experience.
/ ]( J c( M3 ?' \6 w% TAdditional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.5 R7 p, W) A0 V n+ [) M. c
Candidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology. 6 w/ }$ |( F( A( o
Candidate should be familiar with industry standard ASIC design and verification tools and flow.
% u% b) l1 d, l/ U' tGood knowledge ddr protocol and computer system achitecture would be an added advantage.
6 ` r# n1 b! N/ I" W- [% Z; pGood knowledge of Perl and shell programming would be an added advantage. + t: K# H& T/ y L% R
0 Q( _4 ~; e$ h9 ~( mResponsibilities:
0 ]* j, j3 @) P-Understanding the expected functionality of designs.
7 z3 S# g! d& a+ h: H-Developing testing and regression plans. / v* p$ ^; f0 r. a
-Designing and developing verification environment. ! ^: o8 p0 ^' }) T$ j
-Running RTL and gate-level simulations/regression.
# y8 g5 \2 i# g: J" C" h# f-Code/functional coverage development, analysis and closure.& L& g& p: A, n% E0 W
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Requirements:
: [1 ]2 u* K; V; D# `" N6 c' i5 u! HExperience & Skill: 5 Years
) U9 ?1 V3 }: M- l5 @5 U5 E-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.). . X" G& j6 r# k! b1 N0 E" i, j
-Knowledge in ASIC/FPGA design process and verification tools. ) }. k, M6 `' v1 K
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
) {; ]0 Y8 B( y0 t- Scripting and automation skills (tcl, perl, makefile etc) a plus. 2 G% Z. P1 z5 W, b5 Q; ^" D4 L7 ^
-Familiar with C/C++. % T' C |2 B, K/ E; R; S" C" P& v
-Knowledge of DDR protocol a plus. ; [7 t; k5 `0 [, N2 \+ \3 n
-Independent and self-managing. |
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