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LOAD SDC FILE時
" P7 n/ u+ `# j; d9 j$ p% \Astro 訊息
- m( D u7 f" C* a4 t---------------------------------------------------------------------------
) T3 I' E8 J0 }, \ f2 D# \Info: starting Tcl processing
, R* x* K1 y4 o( l5 E$ XInfo: building design object name tables
. ?2 m& D% a5 s3 VWarning: No pins matched 'TOP/test/mul/A[26]' (SEL-004)
+ |" r+ ~, d1 T/ b& R( d! l. ZWarning: No pins matched 'TOP/test/mul/A[25]' (SEL-004)
% o3 J+ F7 L6 r1 w! @( q
& _5 c: l5 o& u! U( w----------------------------------------------------------------------------: E' g; u. V& O$ [- _$ D
SDC FILE( g, R$ g0 `- s8 _' ]
( Z5 G0 D) I0 O8 u+ O
set_multicycle_path 9 -through [list [get_pins \5 w# n: U: e. D% h
{TOP/test/mul/A[26]}] [get_pins \
1 u7 N7 V: ]$ i: f5 a+ m{TOP/test/mul/A[25]}] [get_pins \- X' X9 A9 Z7 J* a( Z" @
/ ~/ L" r- W- Q! {
# G! k) `/ }0 [" J" Y% V) `-----------------------------------------------------------------------------
+ k+ w w" A8 y/ |Verilog File7 m; ^6 s# q4 I& \7 U6 {& J
. k+ |( t: x8 q2 @3 x" M
uniquify_mul_0 mul ( .A(icwAeYfSum[26:0]), .B(
+ |* m' O4 J7 {2 K* [8 ^; U: ~- N/ p icwAeYfNum[18:0]), .C(ae_avg) ); |
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