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Xilinx跟Altera征戰也過了數10年了, 這其間Xilinx理所當然是老大, 然而這幾年間Altera的表現也非常亮麗. 三年多前, Lattice由CPLD老大加入FPGA戰局, 這一段時間FPGA大量的降價, 不能說Lattice毫無功勞.- P- A4 s/ [, X: \2 g* e0 D% K1 m9 d; @/ y+ t
# {# T: y0 T! g& \- Y) `1 g6 J話說Altera老是在和Xilinx嗆聲, 說他的FPGA才是世界最新進的, 底下我收錄了二段"各說各話".
5 N4 N' |' E! U; O! `: v1 d雖然這是典型的一個FPGA各自表述, 但是你有什麼看法呢?
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4 ]1 n7 z0 y& }4 d. Q, XXilinx說法
) Y- m2 j* X; kreference: http://www.xilinx.com/products/s ... x/virtex5/index.htm
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The World's First 65nm FPGA; F4 Y, W2 D1 j" N& \9 ?3 T
Built on the revolutionary ExpressFabric™ architecture, the Xilinx Virtex-5 family is the ultimate system integration platform. With the industry’s highest performance, ultimate connectivity, optimized power, and lowest system cost, you can design next-generation systems for wired/wireless networking, audio/video, storage/server and other markets with maximum productivity' @/ e0 v* L! O* B, M
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Why Virtex-5
' Y8 R8 P7 g+ r! s# v' B8 \The Virtex-5 family of FPGAs offers a choice of four new platforms, each delivering an optimized balance of high-performance logic, serial connectivity, signal processing, and embedded processing. Three platforms are available now: 9 Y- D D; |1 V
5 o6 o% f2 ?/ m9 e+ a- N& MOptimized for high-performance logic9 j, }0 U% Y* ~, |- y
Optimized for high-performance logic with low-power serial connectivity & n" n0 J7 q1 T. f* i/ f. h. Q
Optimized for DSP and memory-intensive applications with low-power serial connectivity
6 |6 n ?8 ?; J# p* u$ C1 Q8 kMeet Your Performance Targets Easily
5 R" w5 H, }, u: j: u9 wAchieve a two speed-grade performance gain with new ExpressFabric technology 3 y4 ]* {$ _/ a( ~) m
550 MHz clocking * n2 r2 Y, U+ G% x
Performance-tuned IP blocks 0 u+ U: V& Z& N( P8 _6 {
352 GMACS from DSP48E slices 6 W+ }! @6 z- e! P
1.25 Gbps LVDS I/O 7 s& W2 x( R. u7 c/ A/ s2 n
More about Virtex-5 performance advantage ; Q4 ~& @6 p/ J& p& R
Optimize I/O Bandwidth, Power and Cost with Easy-to-Use High-Speed Serial Solutions
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/ E( v3 D, b% S100 Mbps—3.2 Gbps serial connectivity
( s! v5 ?) f5 G0 RHardened PCI Express® endpoint blocks and Tri-mode Ethernet MACs
* Z/ c6 ^" s6 gLow power transceivers: less than 100 mW at 3.2 Gbps 8 j' X' Z5 |. c2 k, n4 A) o8 @
Advanced equalization to drive backplanes beyond 40”
) w+ r/ I# n2 R' u& ~Protocol kits accelerate development
* f4 p- f8 ?1 s! e5 y7 L' WReduce Your Power Budget
# l7 |) @6 x& x! h7 _/ o9 e35% lower dynamic power with 65nm ExpressFabric and power-saving IP blocks ; q1 c* d0 j- g+ Y
Maintain low static power with 65nm triple-oxide technology
/ F+ p# u9 W& d: @# h( oMore about Virtex-5 power advantage
4 `! h9 h4 Z# _9 vUltimate Connectivity with SelectIO™ Technology
7 Y5 g/ t0 d( p+ S* R1.25 Gbps differential, 800 Mbps single-ended I/O . E( }3 T% a, _
3.3V support at 65nm
8 H( P ]( @6 j, `7 F5 l: WSecond-generation sparse chevron packaging reduces crosstalk
8 g$ L" L1 T$ f' a- sOn-substrate bypass capacitors simplify PCB design 1 }9 l* l5 E% w& q+ H
More about Virtex-5 SelectIO technology ! W2 z- n. K! ~) X
Reduce System Cost ^& M9 H& K' w+ B& G& Q1 F- u
Choose smaller device with efficient ExpressFabric technology and 65nm ' G& V" j' l8 |# w! h) ]* o# X
Meet aggressive performance targets in the least expensive speed grade ) z: a1 b5 P) e0 {
Reduce part count with built-in, low-power transceivers
L; ]' t) P3 v+ X4 M# J: P: |Increase area efficiency with built-in PCIe endpoint and Ethernet MAC blocks
4 Y0 W! t, m9 x% k- GChoose smaller heat sinks and fans with reduced FPGA power consumption
3 l* U- T1 p7 CAchieve 30-75% cost reduction for volume production using Xilinx EasyPath™ FPGAs
1 q1 M9 P a* h4 Y6 }More about Virtex-5 low-cost advantage
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8 s9 @. |. g2 \+ L/ lAlter的說詞:
$ T4 o; l! W0 `& {7 n) Z* V7 ? f0 ~reference: http://www.altera.com/products/devices/stratix3/st3-index.jsp
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3 s0 V" z! D! _) E n- q; n: f7 w Home > Products > Devices > Stratix III Print This Page
2 w3 k' t/ f0 L2 z. O5 G( Y, ?E-mail This Page 9 ], w5 c0 A* ?( u& h3 }+ n9 l
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Stratix III Device Family — The Lowest Power High-Performance FPGAs' l, u. t, |6 Y0 ~( C6 j$ W
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Highest Performance Highest Density 4 M B8 o2 u1 G6 s! x3 \' U
Programmable Power Technology Enhanced DSP Capabilities
' f' `: P; A9 b; v Family Overview Getting Started 7 n- C2 G' v. f" q1 \; l$ X- G
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Getting started on that next-generation system design? Imagine how much smoother the task would be with an FPGA that gave you the capabilities to implement any design with high productivity and low risk. 2 \7 t( U( J: X) _. L& l- H
5 z& N" e7 D W) y8 i" AWith Altera’s new Stratix® III device family, you get high-end FPGAs that combine the world's highest performance and highest density with the lowest possible power consumption. Stratix III FPGAs provide the high performance and high-integration capabilities needed for next-generation basestations, network infrastructure, and advanced imaging equipment.+ L, A( L+ O. G5 ^# d
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With Altera, you get the devices you want with the features you want when you want them. You also get the collaboration and support you need to design your next-generation systems with confidence.6 c1 E5 ~! g1 Z; h+ i. z
9 N! a) J2 R7 SFigure 1. Stratix III FPGAs Building on the Stratix II Architecture
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/ F2 u! C4 l1 G* Y) x$ e6 M1 p: a( z6 TLowest Power High-End FPGAs: S$ I3 u/ c8 \
To design the Stratix III FPGA family, Altera's product planners began with the Stratix II FPGA architecture. Then, in collaboration with the top technologists from over 50 of Altera's major customers, they defined, designed, and developed the most advanced FPGA architecture for next-generation systems.8 h! J0 B: B9 v% D$ _
* n, l9 `, |! g5 [" I3 v" W* PAs a result, Stratix III devices incorporate features to combine high performance with the lowest possible static and dynamic power consumption—up to 50 percent lower than previous generation high-end FPGAs, including:
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Programmable Power Technology , j! A, b3 r0 L
Selectable core voltage (0.9V or 1.1V)
) C9 X6 I! ~% q/ gProcess and circuit technologies
4 @- Q$ z8 l: q% u' pQuartus® II PowerPlay power analysis and optimization technology l$ ?( c5 X6 E, G
Stratix III devices are engineered for high-speed core performance coupled with high-speed I/O with the best signal integrity in the industry. For example, they are the only FPGAs capable of implementing DDR3 at 400 MHz. This increase in performance is achieved by the implementation of:
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* `# b2 l5 d$ VEnhanced DSP blocks for easy implementation of signal processing algorithms
3 A( F1 A0 g: {5 b- w- \; |5 s) AOptimized internal memory for enhanced signal integrity memory interfaces
r( |8 D3 X, r' @& ]$ r0 YHigh performance external memory interfaces * i+ D1 U# o9 b: C4 ]& m0 l
Enhanced routing architecture
+ O# n6 Y6 i% a3 r1 qI/O flexibility to support the latest external memory standards
* v! _6 G) G" N( hBest Price/Performance Options
1 V! N" O* N5 A V T& I5 ]To give you the best price/performance solution for your design applications, Altera's Stratix III FPGAs are offered in three application-optimized variants:
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Stratix III L devices focus on logic-rich applications
/ i) R- X# k V# h* bStratix III E devices focus on DSP- and memory-rich applications ; V1 n" |/ C& s( b
Stratix III GX devices include multi-gigabit transceivers
7 e& ?. N/ X9 b0 A; D2 c+ O4 P: qHardCopy® structured ASICs provide the no-risk migration path from Stratix III high-density logic to low-cost, high-performance, high-volume production.
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x* g! x0 O! x G. }Advanced Process Technology; z2 C: v/ g* v
Altera and long-standing fab partner the Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), have been working on 65-nm process technologies since 2003. Since then, Altera has developed multiple test chips as part of a rigorous program to ensure that Stratix III FPGAs are successfully delivered on the latest 65-nm technology, in volume, and on schedule.% g# T$ P. J8 q* I' F% f u
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Exceed Performance and Finish Faster% ~2 C2 U) `: o/ }& H/ y4 ^4 y; n
Altera’s Quartus II software gives you the development and productivity tools you need to complete development faster, and ensure you have the performance, power, and signal integrity needed to meet or exceed your design requirements.
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+ C# h8 l* D5 t* QTimeQuest Timing Analyzer supports industry-standard Synopsys Design Constraints (SDC)-based timing analysis methodology to complete timing closure quickly ; I m5 }7 l% C& M
Incremental Compilation supports team-based design providing faster compilation for design iterations while preserving performance
, }4 m3 G1 Z5 P D5 \PowerPlay Power Analysis and Optimization Technology provides automated power optimization to manage power from design concept through implementation 6 C. ]4 W+ g0 h6 l; J$ u9 H4 o
Four Stage Signal Integrity Analysis
3 X0 H8 O# v$ `8 FStructured ASIC Co-Design supports seamless migration between Stratix III FPGAs and HardCopy structured ASICs 8 X4 A5 Y0 l" P9 D
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Altera甚至信誓旦旦整理了一份white paper來說明他的產品才是最好的...' e) l! ?9 s6 ^$ ~ e
http://alter.com/literature/wp/wp-01007.pdf( M2 D5 V) p- V* _+ Y
我這個人是從來都不相信政治語言 , 商人的話更是不可信, 你們覺得呢? |
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