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發表於 2007-2-6 18:17:18
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AMD Geode LX 800@0.9W處理器
General Features( Z" {- P. O. _6 {9 I h
■ Functional blocks include:3 _/ F- t. c5 N. i( G6 \& g
— CPU Core1 K( h9 r% G; }' Q& I
— GeodeLink™ Control Processor1 }( Z0 A; F: U' G3 h# B! d" f* [/ ~9 O
— GeodeLink Interface Units
' U4 j3 g* v, ^1 O# v, Y, {9 j— GeodeLink Memory Controller
7 Y3 t y. ~; w3 }. h+ V5 R6 V, h— Graphics Processor B4 |2 Y3 e3 G( S1 n# f- Z
— Display Controller
" y8 v' E, M- T e! X% m% j— Video Processor) j' A9 {& e, p3 d7 G4 |
– TFT Controller/Video Output Port7 E N2 r* |# e
— Video Input Port
( u2 G/ _ z! E2 e7 c$ A( a— GeodeLink PCI Bridge
% Y0 h4 x) o# v8 {. ^— Security Block
; {0 J* x/ O, { D, z7 q■ 0.13 micron process0 E$ D* E% z+ N7 N
■ Packaging:+ s. w0 P6 H1 t5 U7 ?
— 481-Terminal BGU (Ball Grid Array Cavity Up) with* s/ m5 h$ h, u: r' M* \. B
internal heatspreader+ |: [+ V& j1 l# G/ b( m& F/ x, n
■ Single packaging option supports all features
& K" J/ U* M! mCPU Processor Features
8 H. d' o4 L( l8 @+ U3 R# O■ x86/x87-compatible CPU core
, I3 |7 k3 X$ w! S- b& X■ Performance: a1 I: d* t# |8 u+ r$ h6 x; t9 ^
— Processor frequency: up to 500 MHz2 H& z0 t! Q0 g( E! ^
— Dhrystone 2.1 MIPs: 150 to 450
- ~, y3 I4 U. x- L/ A N— Fully pipelined FPU
- i. s% L7 T- A- v- z& o■ Split I/D cache/TLB (Translation Look-aside Buffer):2 M1 R' h- T. H* @1 x% h4 X, H
— 64 KB I-cache/64 KB D-cache0 K8 _( T0 [) N+ w$ |* c6 O
— 128 KB L2 cache configurable as I-cache, D-cache,5 c4 q6 C8 f, Q1 D+ t# g
or both$ a# H, X5 I+ h6 J8 a
■ Efficient prefetch and branch prediction* U* p& ^9 [8 g! X2 u2 L) o
■ Integrated FPU that supports the MMX® and% k. Z, Z( i& A& F
AMD 3DNow!™ instruction sets
8 x- x: h) a7 x, m8 e■ Fully pipelined single precision FPU hardware with; u! S9 r. ^+ C+ X/ k- [- a" s
microcode support for higher precisions' V2 y2 Q* {' M
GeodeLink™ Control Processor' T. {; D* t$ J& g) [
■ JTAG interface:1 H% V/ O- r& Q: ^
— ATPG, Full Scan, BIST on all arrays. B- m' _# s% ^# B3 J
— 1149.1 Boundary Scan compliant/ ~6 P- X% S( X" l/ w3 p- c, I
■ ICE (in-circuit emulator) interface9 k8 E* T: i6 O4 d4 D N
■ Reset and clock control
. J$ B8 s' F: l" F4 @, M■ Designed for improved software debug methods and
1 a j% r1 }% k" Vperformance analysis% Y7 |$ H3 K9 X M) M( v
■ Power Management:
% z' n. L" }4 u7 `* r; T* w; C: v— Total Dissipated Power (TDP) 3.8W, 1.6W typical @
0 {* S0 {* M! Q& w500 MHz max power
' a4 e' v& ]+ y8 z; ]— GeodeLink active hardware power management/ f' Y# j& Z1 t6 O0 V: |. K
— Hardware support for standard ACPI software power& c; k& t" `8 _% Y f
management& s+ H7 D2 t' `2 i0 V; C2 @7 |1 n
— I/O companion SUSP/SUSPA power controls
% m& o e7 U4 f8 c1 b$ x— Lower power I/O% E u0 C7 B% q) [/ Y8 x
— Wakeup on SMI/INTR
$ [ K" O" h: e$ S8 v! S■ Designed to work in conjunction with the3 O1 ~) E$ c! Z5 E0 `( W
AMD Geode™ CS5536 companion device2 S/ p/ X0 s( j5 v
GeodeLink™ Architecture' h5 g3 U+ c" h) |* w
■ High bandwidth packetized uni-directional bus for" C# H% @. o: J' C, X# N9 R
internal peripherals
! A* F7 J, C0 u8 B7 V3 n! f■ Standardized protocol to allow variants of products to be
$ F" X8 f' [1 m# x8 X. edeveloped by adding or removing modules( s! y) u& j# J! C
■ GeodeLink Control Processor (GLCP) for diagnostics
2 U" f O9 \* }7 }" C" B9 Eand scan control- O* r8 h# v: W8 s+ g& Q
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect3 s" d/ ` ^ \
GeodeLink™ Memory Controller
9 Y1 E7 r3 Z( Z9 z. f& z ^■ Integrated memory controller for low latency to CPU and: w- J4 J$ D" Z7 A% A
on-chip peripherals
9 v, ~( m# O4 d. g2 w7 S$ i. D- I■ 64-bit wide DDR SDRAM bus operating frequency:0 }1 F" `1 ?* ~* S q' T
— 200 MHz, 400 MT/S
}8 C# O# k" w8 @$ c" V■ Supports unbuffered DDR DIMMS using up to 1 GB
L& m4 G. j$ ODRAM technology
6 Q& c1 t9 T) Q■ Supports up to 2 DIMMS (16 devices max)
x$ |# J, q5 r( ^: N8 k* s5 |7 S2D Graphics Processor
- i5 y* p( V/ s, C6 S■ High performance 2D graphics controller* X* B1 e# b0 j; Y0 S) W
■ Alpha BLT
% r9 e3 m; d) Y# I" C2 \ u G, i* O■ Microsoft® Windows® GDI GUI acceleration:8 K5 |( \: w% P. F0 O9 R
— Hardware support for all Microsoft RDP codes
4 k" Q' v& j/ A! u. ?■ Command buffer interface for asynchronous BLTs9 L- e* v+ w! W4 M! _- o
■ Second pattern channel support9 r) P4 a+ d' m5 k# z, t ]& `0 s
■ Hardware screen rotation |
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