ASIC設計工程師如何保住飯碗？

ranica

Senior ASIC engineer
7 s% x) H8 d8 T8 Y  m客户 a start up company with innovative technology
地点 Shanghai

职位要求
  ~( j1 Y5 }7 _& F. A  V% C1 t5 + years experience in ASIC design -> must
& c! d3 q' B! @4 }- f$ I/ X) E· MS in Electrical Engineering (or equivalent) is a must have
· Experience with WIFI baseband/MAC or related wireless baseband technology desired -> plus
8 f! H# r% S9 m+ v9 l/ G· System on Chip (SOC) Integration Experience, including AHB/AXI, CPU integration -> plus
· Experience with interfaces such as SPI, SDIO, USB -> plus
· Working knowledge of networking protocols such as TCP/IP, 802.3, 802.11 -> plus
· Must be expert in Verilog RTL language -> must
· Must be familiar with the ASIC design flow from RTL through synthesis, including the tool flow. -> must
· Verification experience – Verilog, System-Verilog, Coverage Analysis -> must for verification engineer, plus for design engineer
· FPGA emulation experience -> plus
· Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging -> plus
# P! ?8 `3 W4 }/ e2 w9 [' k· Experience with digital backend

ranica

资深数字设计工程师
客户 A start
- l+ ^, P, Z0 {3 x. ?6 G地点 Shanghai
9 i* [2 U/ ]6 ]6 s. d9 G3 N! V
职责:
参与从产品定义到量产的整个流程。
参与芯片架构定义。
1 Z1 j, q- p5 Z" y! EASIC设计，RTL编程和RTL仿真。
综合和FPGA评估。
与应用测试工程师合作，提出最优解决方案。

, ?' {$ v/ a# h; F( D: I职位要求：
电子工程相关专业硕士毕业。
# L* I5 S: Y/ J7 C: @2 [3 C) }; g3年至5年以上RTL设计经验。
& P$ I9 W0 c" h* D' t! m有音视频领域经验优先。
% L% D# z- [8 t0 H5 a5 M2 U: z8 S良好团队精神，学习能力强，敢于接受挑战。
必须具备RTL编程、仿真经验。
! M% F: _, c* \+ P  u* v$ A' P熟悉FPGA验证优先。

ranica

资深数字设计工程师
) _2 H7 @: d. e+ b, x
* l, I, `3 C+ j公      司：NO.233-A start-up company
+ }( v# H/ ?1 @/ D工作地点：上海

职责:
! }' V- V5 |0 |/ G' }5 R参与从产品定义到量产的整个流程。
+ ~: s- A- Y9 f  \. M. l参与芯片架构定义。
ASIC设计，RTL编程和RTL仿真。
1 g+ n2 y+ b2 Y- A5 g- d# S3 T- b综合和FPGA评估。
与应用测试工程师合作，提出最优解决方案。
& _1 X' h2 H" y% [2 o' |- w
- l+ v! d: q$ d5 x% i. E4 O要求：
/ C" v# \" ^0 X( F$ I电子工程相关专业硕士毕业。
. u7 Q8 N  [3 y1 [- o3年至5年以上RTL设计经验。
有音视频领域经验优先。
良好团队精神，学习能力强，敢于接受挑战。
* u- e- j' v2 o. q必须具备RTL编程、仿真经验。
熟悉FPGA验证优先。

tk02561

安森美半導體與空中巴士完成合作開發用於A350 XWB 飛行控制電腦的複雜ASIC
. b3 \& j  Z2 I& V5 X安森美半導體的110 nm製程技術平台達致開發關鍵航空應用的高度可靠方案

/ q: \3 H$ v# E0 B7 U0 Y" I( a5 N. w2013年6月17日 – 推動高能效創新的安森美半導體(ON Semiconductor，美國納斯達克上市代號：ONNN)與領先的飛機製造商空中巴士(簡稱“空巴”)完成合作開發及投入生產一款複雜的專用整合電路(ASIC)，應用於空巴A350 XWB寬體飛機的飛行控制電腦。這定制硅方案的代號為JEKYLL，使用了安森美半導體內部的110奈米(nm)製程技術，在安森美半導體美國奧勒岡州的Gresham工廠製造。JEKYLL項目的完成，反映了雙方從可行性評估到第一次即對原型到按期為A350 XWB量產的成功合作。
% Q% h+ W' A+ Y* z, v
此ASIC的設計符合D0-254航空要求，並滿足空巴嚴格的可靠性及產品長壽的需求，為空巴A350 XWB飛機的飛行控制主電腦提供優化的性能。安森美半導體被選中參與這個項目的原因有多種，包括公司在複雜ASIC開發方面的專業知識和技術、著力於軍事及航空應用、一流的品質水準、毫無疑問的長期產品支援，以及對D0-254要求的深入瞭解。
, E3 ~- [- f/ Z' x& J. r0 e
安森美半導體軍事/航空、數字、晶圓製造、整合式被動元件(IPD)及成像感測器產品分部副總裁Vince Hopkin說：「能成功開發這複雜的ASIC是空巴與安森美半導體通力及詳細的合作成果，彰顯我們致力於服務講究高可靠性的航空市場。我們公司內部的110 nm技術極適合於此要求高性能的應用，是我們從40 nm到0.35 µm之強固技術方案組合的一部分。」

( M, W3 ^2 |/ H4 N2 l歡迎蒞臨安森美半導體於2013年6月17日至23日在2013巴黎航展的展台(2B館H58展位)。更多有關此航展的訊息，請參考：http://www.paris-air-show.com/。

ranica

Staff Digital Design Engineer
公      司：NO.82-A famous IC company
" a) Z. S! w, L! u; \$ y* b工作地点：上海
9 P6 D3 O& l$ h6 R# |
, d7 [3 a- R$ m, ^3 t职位描述
A worldwide leader in the design and manufacture of microcontrollers, capacitive touch solutions, advanced logic, mixed-signal, nonvolatile memory and radio frequency (RF) components. Leveraging one of the industry''s broadest intellectual property (IP) technology portfolios, be able to provide the electronics industry with complete system solutions focused on industrial, consumer, security, communications, computing and automotive markets. As a global company with 5,100 employees worldwide, she operates in more than 40 countries and has 30 design centers, including locations in Shanghai and Taipei. Her solutions enable their customers to lead the markets they serve by creating products that are more powerful, smarter, energy efficient, lower cost, and more versatile than ever before.
, E' d  g5 h2 @. c$ @8 k8 v
Responsibilities
6 A1 b* i! _/ q  q• Develop ARM-based MCU/SOC products
职位要求
) `7 y: m' t4 }8 |Mandatory Skills
' R' T2 N1 k, }2 I# r/ X        Very good Verilog coding and simulation capability.
: C6 V2 Y7 H) e9 J; h. {5 E; N5 O Familiar with ASIC design flow, including related tool experience and skill, such as DC , conformal , formality , Tmax or PT.
+ P; T5 z. |. Y        Fluency in English and good in communication skill.
Preferred Skills
        ARM-Based MCU or DSP related experience and knowledge is highly preferred.
        Understanding of embedded firmware and programming is a plus.
        Unix/Linux shell/script programming.
Education
Master Degree of EE or related.
" }( ?3 s$ q9 q7 P* RExperience
1 E% \% w" L1 N0 N; o* a& @. H        8+ years of design experience.
; g& L7 @& Z' J( B! ~3 D% J        At least two years of US or Europe-based company experience.
' |7 M1 Z5 w( [. L, cPosition: Regular
( l; G- a6 z1 w# ~+ K: T! ~8 ~9 mShiftay
: u) N  g6 m& r: d1 w/ ^- ILocation: China

ranica

ASIC Design Manager
公      司：a provider of highly integrated semiconductor company
工作地点：北京
& u4 x' r* o6 u
Description:  
Roles & Responsibilities:
In charge of logic design from spec to tape out and bring up  
+ a7 d% S# b& {% f+ T. |Micro architecture and implementation  
Working on or lead logic design, simulation, validation  
Coordinate analog design, bring up and thouble shooting
* h6 H9 [- |. D( y; a; f  z
+ h7 x7 A3 J2 ], X' cRequirements:
, o0 r: T% f  R& t4 Q5+ experience on IC design  
& e4 y  L# g: {; z7 ~, R  a8 p5 sDeep knowledge and skill on ASIC design flow including RTL coding, simulation,  synthesis, timing closure, power estimation, formal validation
4 e  b# R3 v& h( vDeep knowledge on digital baseband or SoC design   
Master degree or higher.  
9 E: y! u+ O' u! a7 wIt will be plus having experience to lead and deliver ASIC project

ranica

数字工程师
5 k4 P5 S: L0 X' o
  `& [/ C* @6 p4 Y* a7 g公      司：IC设计公司
1 _9 f, i  E4 P: [1 N工作地点：深圳
' j$ s, I& N9 b+ S; I
2 s# I6 V( c) \( G: z0 r职位要求
1、 熟悉数字电路设计流程方法及工具；
/ C: ]  k: H$ \  y: y2、 精通LCD数字电路设计；
3、 具有两年以上MIPI设计经验。

ritaliu0604

资深变频空调方案研发工程师

2 N3 I; n. Y% Q* y! u  v" F% b公      司：A famous IC design company in shanghai
工作地点：上海

职位描述
從事變頻空調控制軟件的研發。

职位要求
2 O& A3 q7 j" x2 B7 u" [  X4 F7 G有變頻空調控制軟件的研發經驗，熟悉變頻空調控制算法及相關技術

ranica

ASIC Design Engineer

& p3 d$ S. @- X* \* r& y6 i公      司：A famous IC company
工作地点：上海
" B' q1 H$ @, h- B) P$ |/ {; g
The Role:
' ~/ I# N2 _* u! }·         ASIC design  
" Q$ q& x& }6 c·         Work closely with the California teams
5 t, A  d8 M* z% @·         Support chip tape out and bring up
1 E4 ~+ B/ c0 C) y
Requirements:
·         3+ years experience in ASIC design
·         BS in Electrical Engineering (or equivalent) is a must have, MSEE is desired
) O4 L3 {' C( \$ h3 a+ l" g* K·         System on Chip (SOC) Integration Experience, including AHB/AXI, CPU, Interface integration
0 d' ^) I9 E9 l3 j: X; s2 j0 O5 D" l·         Experience with WIFI or related wireless technology (i.e. WIMAX, 3G, LTE, etc.) is a plus
·         Experience with interfaces such as PCIe, Ethernet, DDR, USB
·         Working knowledge of networking protocols such as TCP/IP, 802.3, 802.11
* r3 F. C% s1 V4 [" r- p·         Working knowledge of C programming language
·         Experience with Medium Access protocols a plus
·         Must be expert in Verilog RTL language
·         Must be familiar with the ASIC design flow from RTL through synthesis, including the tool flow.
( ~/ v- i: |/ l5 e7 n1 q& M·         Verification experience – Verilog, System-Verilog, Coverage Analysis
·         FPGA emulation experience
' {& U! J) k0 W' z- B·         Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging

ranica

IC PM

公      司：A famous European IC company
工作地点：上海

/ s. q% Q+ k6 z. t" s4 SRoles and Responsibilities   
1. Manage ASIC design project according to product development process   
     - Coordinate the different resources to deliver the ASIC product in time and with good quality  
     - Responsible for the communication of the whole project team  
     - Participates and drives internal review of each development phase and make proper justification  
) @: N5 }2 {( `. g( K8 h# w     - Develop and manage project schedule, resource, communication and critical path  
4 G$ s, B- h$ c) g$ f     - Identify risk and develop mitigation plan with the project team  
2. Closely work with IC manufacturing and testing / qualification to drive the ASIC products into mass production in time and with good quality
3. Work with the financing and control the project budget
. H; W; `: R# ]
( P; r  w( M3 G1 k+ ]: L7 [7 F' pQualification Requirement   
- Master degree or above in Device Physics, Electrical/Electronics Engineering or equivalent  
- 4+ years experience in the semiconductor industry in relevant R&D departments.  
1 @- M9 [5 ^+ Y; b2 O) T- Preferred to have at least 1 successful tape-out experience as project manager  
- Knowledge of ASIC Design from front-end to back-end (Analog design, RTL, Synthesis, STA, floor-plan, P&R, package, testing, etc.)  
- Basic leadership of team for allocation of tasks   
- c9 ?: J4 U6 j0 t# v2 p0 c- `- Management experience with subcontractors  
- Good English, excellent communication skills and team spirit oriented  
& x5 E" K& Z' c3 @& j$ V( s1 z; A- Self motivated, strong communication and interpersonal skills

tk02561

ASIC工程师
公      司：High-technical IC supplie with commercial FPGA intellectual property
工作地点：北京

: I4 h) @2 ^  S% k7 x8 k+ _/ w+ A职位描述
1.微电子相关专业硕士学历, 3+年ASIC前端工作经验（不含在校、实习）;  
2.熟悉并参与过ARM或MIPS等常用SOC架构的设计、应用,对SOC架构及常用外设的工作原理有深入理解。
& k4 f, l4 [+ Y& j. J3.精通verilog语言，能够独立完成verilog module design，拥有良好编程习惯codingstyle。
2 o2 Y; J: ?# m6 r4 b4.能够独立完成单元级仿真，在系统仿真中承担部分工作。
5.至少1次成功流片经验。
0 Z# k% m8 w( V3 n# _6.对synthesis、sta、dft等有一定了解。
. C3 l' e# x6 N& R8 I, B3 V7.良好的团队合作精神

6 V! y" U8 j$ A职位要求
全部或部分满足以下条件者优先考虑：
1.有在大型asic公司工作经验，深入理解其企业文化。
8 `8 S& y6 e8 ?2.熟悉验证方法学;熟练使用SystemVerilog等专用语言进行验证平台的搭建和维护。对Testcase规划、覆盖率分析、门级仿真、ATE testpattern产生等有实践经验和深入理解。
6 Q9 R, N6 q& z/ R3. 丰富的fpga emulation经验，能熟练进行板级debug，编写调试简单driver。
4．对芯片系统架构有一定理解，能进行子系统级别的独立规划设计。对以下知识中的至少2种有实际经验：
. J, |& n9 c/ p/ D5 F( bARM/MIPS/8051 CPU及其架构,
AMBA(AXI/AHB/APB) 总线、OCP,  
USB(3.0/2.0/1.1,  
# R$ e, ~# B4 f. s  |1 kNAND/Nor Flash/S-flash controller
DDR（2.0/3.0）controller/PHY
6 N0 x- r( Y. {low power design,  
chip level clock/reset generation and control,  
  E' p% w. Z) k! c1 M1 U6 oSD card controller, SATA,sim card  
3 a& e; ]- }/ O2 s4 gsoc基本外设 (SPI/ GPIO/timer/WDT/I2S(SSI)/I2C/UART),
Ethernet,  
JTAG, etc.

ranica

ASIC Digital Verification Engineer
5 W( T( k0 u* z5 }0 }
$ ?  _8 g) v3 z/ f6 g2 J公      司：A mobile chipset semiconductor company
0 R4 @4 e; S3 m+ s) t工作地点：上海
% r* _9 \- W/ q) [" l/ p
; ^* u$ w/ H. v$ k1 L. }" fResponsibilities:  
  Make verification plan for one module or whole chip.  
  Build up and maintain module-level and chip-level verification environment  
  Verify ASIC digital design based on case list, and output verification report.  
1 k7 p0 f8 o5 O$ g: [# Z4 R  Also responsible for lint checking and formal verification.  

Qualifications:  
  Proficiency in logic verification.  
4 K- k" [9 |; y& k$ Q6 g  Experience with Verilog logic design language.  
. v& X2 }' ]8 Z  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.  
  Experience with UNIX/Linux simulation tools such as IUS or VCS.  
) W. F3 Y# Q2 a! ]4 u1 j( s7 A; a  Experience with C and C++ is a plus.  
* X3 h( a/ S, s4 l1 S( w+ E  Experience with C_SHELL, TCL or PERL is a plus.  
% E: u) ~  }: f' W( @  Experience with UVM, OVM or VMM is a plus.  
  t( \8 N; W* Y0 d  h: m: s  Good knowledge of SOC design is a plus.  
3 p8 g( Q: P7 k" w0 ^4 l- y  Good knowledge of software design is a plus.  
2 ^3 @$ }* H6 P0 X: J5 K  Self-motivated and good team player.  
  MSEE or BSEE with 2+ years.

ranica

数字芯片设计工程师（DFT/综合）

公      司：A mobile chipset semiconductor company
0 l) N; Q$ ~- W* `: s工作地点：上海
! x0 K+ I% M8 }9 |
( J0 j7 Z* r. U6 e- \职位描述：
" E& U2 x) F1 L7 i1、To provide and support SYN&DFT work for several projects in parallel  
2、Run block level implementation for each project, include synthesis, DFT and LEC
  Z/ }7 q) U7 F2 d4 @4 m3、Support block level physical evaluation  
0 k4 h$ s2 ?8 [; l4、co-work with designer and provide block level SDC file
0 o, |5 D2 x7 F# }  T" V- u8 g5、co-work with Back-end team for timing signoff
6 K( a) a) J( B4 t$ N' W9 I
  \7 q4 X; o( f1 Z职位需求：
1. 了解集成电路设计的基本流程
9 e) q* `4 ~/ A- t* g5 ~2. 相关Synthesis, formal check 和DFT的工作经验。(3A, 3B, 3C精通一项即可)
3A. 有超过2～3个项目的synthesis 经验， 用过RTL compiler且熟悉timing的相关知识  
/ a2 y" t+ z6 ?% Y$ J& G: ^3B. 有超过2～3个项目的formal check经验，熟悉CPF的low power flow
& y2 E9 u( T) l$ ~, \3 U! C3C. 有超过2～3个项目的DFT insertion经验， 用过Mentor DFT的优先考虑
3. 具有良好的英语阅读和书写能力。

globe0968

IC PM
公      司：A famous European IC company
工作地点：上海
7 s* d# u* D7 X( q- E3 y: f
Roles and Responsibilities   
1. Manage ASIC design project according to product development process   
/ t- T9 l5 J  I: Q# A3 _- V7 f     - Coordinate the different resources to deliver the ASIC product in time and with good quality  
     - Responsible for the communication of the whole project team  
     - Participates and drives internal review of each development phase and make proper justification  
     - Develop and manage project schedule, resource, communication and critical path  
! K. }. ~2 p# F$ `: G. Z) N0 k$ i  R     - Identify risk and develop mitigation plan with the project team  
$ W8 y& R6 S( t9 P2. Closely work with IC manufacturing and testing / qualification to drive the ASIC products into mass production in time and with good quality
' [' {$ Z* w) I, p3. Work with the financing and control the project budget
% A6 r' N) u- I- e' j% U
Qualification Requirement   
- Master degree or above in Device Physics, Electrical/Electronics Engineering or equivalent  
- 4+ years experience in the semiconductor industry in relevant R&D departments.  
- Preferred to have at least 1 successful tape-out experience as project manager  
- Knowledge of ASIC Design from front-end to back-end (Analog design, RTL, Synthesis, STA, floor-plan, P&R, package, testing, etc.)  
- Basic leadership of team for allocation of tasks   
# [5 O2 F9 O* U: _8 ]6 o" D! M$ P; _7 o# r- Management experience with subcontractors  
: `) `- v  Y$ A- Good English, excellent communication skills and team spirit oriented  
- Self motivated, strong communication and interpersonal skills

ritaliu0604

数字芯片设计工程师（DFT/综合）
公      司：A mobile chipset semiconductor company
9 j" |2 E2 X. _/ n  D工作地点：上海

职位描述：
1、To provide and support SYN&DFT work for several projects in parallel  
7 R- g! L' w, H* F- W+ J$ [8 u2、Run block level implementation for each project, include synthesis, DFT and LEC
3、Support block level physical evaluation  
" o/ G6 {, p- s" P: d$ I4、co-work with designer and provide block level SDC file
$ G' e4 P' x0 E7 s% r0 ~* K4 Q  U5、co-work with Back-end team for timing signoff

职位需求：
. l6 W0 R) O1 o7 J$ v; m1. 了解集成电路设计的基本流程
2. 相关Synthesis, formal check 和DFT的工作经验。(3A, 3B, 3C精通一项即可)
3A. 有超过2～3个项目的synthesis 经验， 用过RTL compiler且熟悉timing的相关知识  
3B. 有超过2～3个项目的formal check经验，熟悉CPF的low power flow
6 p; v- M' f! T4 V3C. 有超过2～3个项目的DFT insertion经验， 用过Mentor DFT的优先考虑
' _  t: G! i) c& p  ?/ @$ F3. 具有良好的英语阅读和书写能力。

ranica

资深数字IC设计工程师（图形图像方向）
公      司：A famous IC company
工作地点：上海
" `. `7 {/ N+ C; ?4 x$ a$ z
岗位职责：(图形图象处理和视频编解码方向)：
) e: w& a7 I/ s: ^* a5 l+ E/ {7 h1、根据市场需求和芯片定位，参与并带领团队完成图形图像处理或视频编解码等复杂IP的设计验证和交付；
3 A+ g9 o7 J6 c2 W2、对项目进度和质量负责，组织具体技术难点或紧急任务的讨论和攻关，协调其他团队共同完成SPEC的制定和收敛；
/ _$ C# G6 D+ `7 w/ O5 ]
岗位要求：
6 u( f; s' \' k$ X% M1、硕士及以上学历，电子、通信、计算机或微电子专业；
2、有至少两年以上图形图像或视频编解码等领域的IP设计经验；
- f* o  \' C5 T. q3、具备丰富的图形图像处理或视频编解码等相关领域的系统知识
4、具有扎实的数字芯片设计基础，熟悉IC设计的整个流程；
5、具有良好的沟通能力，较强的协调能力，以及团队合作意识；
6、有团队管理经验者优先考虑；

ranica

数字IC设计工程师
公      司：A famous IC company
, k# l/ w6 [$ F% e工作地点：上海
0 Y0 L# E. W& R* T1 q
1 V$ w0 d" \5 j3 V% r, s岗位职责：
, a: p. j- ^( V5 L# R" t3 B% I( Q% k9 \负责各种IP（图形图像接口、图形图象处理、视频编解码、DDR存储接口、Flash接口、USB接口等）的设计、时钟复位模块的设计或者SOC相关的集成设计、系统设计、架构设计。
. o+ u3 }+ v( |" y% {' d: ~
# w# s6 ?" H2 f+ s; g% X% H+ t职位要求：
1、硕士及以上学历，电子、通信、计算机或微电子专业；
2、熟练掌握Verilog、SystemVerilog等语言的编程，有扎实的数字电路基础；
8 v0 p3 Y% L* C( o* k; n3、有1~2年的相关工作经验；
5 m. g$ b1 \/ I' [8 `7 r. M4、具有较强的学习能力、沟通能力和良好的团队合作精神；
5、在以下相关的模块或接口（其中之一）有一定的工作经验：图形图像接口、图形图象处理、视频编解码、DDR存储接口、 Flash接口、USB接口等
6、有大型SOC芯片的研发经验者优先考虑。

ranica

Sr. Staff to Principal Engineer/Mgr
公      司：A famous IC company
工作地点：上海

Job description
9 u: Y7 H9 e5 P5 u6 e6 ?$ o- tThe candidate will be responsible for the architecture and ASIC design and co-verification of various 802.11 wireless baseband IPs within current and next generation wireless products. The candidate will work within the local DSP/digital development team and closely with system/simulation/verification/RF engineering teams in US to develop and implement DSP/digital blocks to build WiFi IPs.

Job responsibilities includes: spec development and design of DSP/digital blocks, developing co-verification platforms, performing simulations, and solving integration and testing problems during the development, characterization, and production stages of the product. Successful candidate must have the ability to communicate with engineers of various backgrounds: systems, software, digital hardware, RFIC design, and verification

ranica

职位要求
; J1 ^4 ~5 g5 C?Extensive hands-on experience in the development of WiFi baseband IC design. The candidate must have at least 8-years development experience on WiFi 802.11 a/g/b including minimum 3 years on 802.11n/ac.  
?Deep knowledge and good understanding of: digital communication theory, information theory; specifically on: equalization, Fourier transform, spatial-temporal coding, linear and maximum-likelihood estimation, Viterbi decoding, frequency/ timing estimation and calibration, automatic gain control, transmitter beam forming, diversity combining, and their high-speed DSP/digital implementation.  
?Extensive experience with RTL programming languages.
?Experience with verification methodologies and tools and advanced complex RTL/C test-bench developments. The familiarity with UVM environment is a plus.
( E$ Q  ^# O5 \& D  O4 I' I?Experience with developing algorithms in C, C++, and Mat lab.
1 N) O$ w! R3 J- i1 t8 }?Experience with scripting language such as Perl, Python.
) ?& Q; ]! J9 P! R?Must have experience with lab testing and characterization of digital sub-systems.
?Candidate must have strong English communication skills with willingness to interact with various groups within the company.
1 P. k: z9 J) s+ n9 y0 P?Experience with physical design flows, tools, methodologies, and development of timing constraints is a plus.
?Familiarity with flows and tools for co-simulation of RTL and C models is a plus.
?Familiarity with testing and integration of RF and baseband systems in the lab is a plus.
8 R" z: f: Y4 E5 ?. a7 x/ d  B/ E?Experience with implementation of calibration modules for RF/Analog blocks is a plus..
?Typically requires a Master degree and 8 years of experience or a PhD and 5 years, in VLSI/ASIC architecture design or ASIC implementation of digital signal processing function.

ranica

Senior Digital Design Engineer
$ z1 Y/ `/ Y; P7 `! U7 ~; S
公      司：A leading semiconductor company
( D/ S2 h2 O: W2 z! n8 [工作地点：香港
- X0 K+ u" r1 P; H( {* J7 a, @% I
Job Responsibilities:
( }, f7 X4 m& u% U4 }; L& w5 I    Perform logic design, RTL coding, design verification, logic synthesis, DFT and static timing analysis
    Develop verification environment and coverage closure
+ {/ ?% C9 D  q! a% Y0 r7 J    Support wafer level testing and silicon evaluation
% G1 x! A- J* J    Prepare technical documents
' _6 p. ~5 z' r1 y% e$ z/ U& Z
! {! s, x9 C  h# G9 H" xJob Requirements:
    B.Sc or above in Electronic Engineering or equivalent. Applicants with postgraduate degree would be considered as an advantage
' d0 [: e* h6 C6 ]    5 Years or above of solid experience in one or more of the following areas: Verilog-based logic design and synthesis, constrained random    testbench with System Verilog & UVM, assertion based design verification or circuit-level SPICE simulations
+ a0 ?: F( r5 j; P# Z' |+ i5 |    Knowledge of SoC and embedded system.
    Knowledge of scripting languages such as Perl, TCL and Make
; [4 i; V5 r2 i6 `0 n    Candidate with less experience will be considered as Digital Design Engineer