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發表於 2008-11-26 21:59:05
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IV. CONCLUSION
/ ~/ Q4 R/ }' HThe designs with 3-stage-inverter and 1-stage-inverter( E p. d w/ l, m: t
controlling circuits have been studied to verify the optimal
+ }& _/ j# j& k" \% Z Kdesign schemes in NMOS-based power-rail ESD clamp
, J4 Y$ M) J9 G" t/ w, R! ^circuits. In addition, two ESD clamp NMOS transistors,$ N" G6 ?' I2 j5 ~5 p
having snapback and no snapback operations, also were codesigned& G! J5 V! q2 U5 L: S9 t& \
with different controlling circuits to realize the' e( }3 g' Y/ u/ w" i' [
impact on their required performance. According to the( f& x4 L* [; P- B
experiments and analyses, the 3-stage inverters can slightly
, o6 A: j8 l$ {6 mincrease the ESD robustness, but they also can dramatically3 P/ H4 }4 m4 z: Z7 F, M; [ V
sacrifice the mis-trigger and latch-on immunity. The 1-stage' S- _- y K* B }
inverter should be an appropriate and reliable candidate for the: s* G. S' H6 A5 I9 K0 G( M
power-rail ESD clamp circuits. |
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