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發表於 2008-11-20 11:53:00
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On-Chip ESD Protection for Integrated Circuits4 y/ F* h/ n' y) N2 z) z& r9 a
An IC Design Perspective
0 I; X3 Q# U8 E, a# f8 M
% f1 z& `! T* [9 B! m9 Mby
; T7 H6 b! A- V+ ]Albert Z.H. Wang
. m, [5 r) b' E3 f" H8 I! iIllinois Institute of Technology, Chicago, USA" P: M5 C" ^. E8 `& u: g, n3 g
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Dedication.
) Y5 I# @! c3 E- rAcknowledgements. & H7 e% h9 o% g' |" m# ~
Preface. # R- }8 m5 {* B# j" t- ~
1. Introduction. 2. ESD Test Models. 3. ESD Pr& p) Z) ?! f' ?) p8 X$ C& B; N
Device Solutions. 4. ESD Protection Circuit Solutions. 5. Advanced ESD Protection; Mixe
{1 {$ p: O; J' r( M3 x4 ]and Whole-Chip ESD Protection. 6. ESD Failure Analysis and Modeling. 7. Layout and Te, j5 [* s0 E4 W" E. T) q& X, s
Influences on ESD Protection Circuit Design. 8. ESD Simulation-Design Methodologies. 9
7 x; H+ X; h% q8 G' \+ \5 mCircuit Interactions. 10. Conclusion Remarks and Future Work.
8 H9 Z3 C8 ?& I8 @; zAppendix A: Summary fo
5 y# e% p9 \/ b* E! M. RStandards. References.
& B8 s+ n0 D A6 m& ?Appendix B: Commercial ESD Testing Systems. # B, O7 b; l! n4 G( N. f3 Y
Appendix C: E
7 ~0 V) |0 B2 z q1 mProtection Circuit Design Checklist. Index. |
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