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CMOS Transistor Layout! Y" I5 L! W# ^) o, l; ~
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Copyright © 2005
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Table of Contents
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Preface
5 W; t1 R- v2 s* O% J, s/ N1. Introduction .................................................................. 1
6 ~* T, Z1 v9 Y8 H! `2. MOS Transistors ........................................................... 2/ u# E9 @* U7 b; u- D- E, q; F% u
3. Fabrication of MOS Transistor ..................................... 57 W+ n+ \/ R- w; N. I, ]* X! Z$ _' ?
4. Layout a Single Transistor .......................................... 11
t- D* C4 `3 _First Stroke The basic transistor layout ..................... 12. ~. @. e7 H6 o; @! I
Second Stroke Compact the transistor layout ................ 13- F ~, d% H9 N
Third Stroke Speed up the transistor ........................... 17
) ?/ L% [' g. mFourth Stroke Clean up the substrate Disturbances ...... 20
9 s3 W. l- V4 p" B/ L4 Y s- s* t9 DFifth Stroke Balancing area, speed and noise ............ 26. `, M1 Q2 z. K7 @. e7 J) Z$ e% a& ~ ~
Sixth Stroke Relief the stress ...................................... 29
, s+ H ^- s/ `3 ?Seventh Stroke Protect the gate ...................................... 30/ z2 _5 X- e* h
Eighth Stroke Improve yield ..........................................328 C6 d: d& R0 O5 m* c: E8 x
5. Layout Several Transistors ......................................... 34
. {* W2 ~* L/ j _Eighth Stroke Improve yield...........................................35
: p' j' F# j2 g& J A. {/ ~# _# s! URe-visit/ M: ~2 s V8 W- E2 P+ m- _
Ninth Stroke Close proximity .......................................36
. ]% P/ C; a) ?/ b$ H: X4 NTenth Stroke Interdigitated layout ............................... 36
$ m" z2 d$ `2 Q' |9 wEleventh Stroke Dummy transistor ................................... 41
# R. |0 O3 p5 P0 u/ }Twelfth Stroke Two-dimension interdigitated layout ..... 43: X: P I* W. m& Z- t) n, A( Q
Thirteenth Stroke Guard ring for the matched transistors ... 45
& A( x1 W: i4 l4 X& _Fourteenth Stroke Keep NMOS away from N-well ............ 45
" t$ l- u9 c1 A0 r, t* LFifteenth Stroke Orientate the transistor ........................... 46
/ k# t' ^, i* tSixteenth Stroke Match the interconnects ......................... 47
3 Y( C- g$ X7 g4 PSeventeenth Stroke The unmatchable .................................... 50
0 T9 `. ~0 V, }) [+ h8 K; j6. Verifying the Transistor Layout ................................. 52
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1 p" r% I# w9 u1 q; m, D[ 本帖最後由 semico_ljj 於 2008-11-1 04:01 PM 編輯 ] |
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