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8 Failure Modes, Reliability Issues, and Case Studies 228
+ T5 R- q& W' D) A& k8.1 Introduction 228# V) j, j9 R$ H. T$ J6 ?/ x
8.2 Failure Mode Analysis 229
/ w2 X% U. g. |& G, r* P8.3 Reliability and Performance Considerations 2381 u$ O% P, O8 ~2 L# ?7 w
8.4 Advanced CMOS Input Protection 239
7 Z# g( G. m. }9 Y8.5 Optimizing the Input Protection Scheme 242
# J/ f+ k8 h3 z% X/ |8.6 Designs for Special Applications 249
- m. \9 T" X1 c) u, G' Y, g8 m5 x8.7 Process Effects on Input Protection Design 253
4 g' a2 n7 U& C) j+ K# t, M; R/ m7 g; O8.8 Total IC Chip Protection 255- D5 D% E% j: C6 [; q! ?& X: \
8.9 Power Bus Protection 256
. Y$ E' r: Z# T: I$ z l9 M' t8.10 Internal Chip ESD Damage 258
* k1 f6 k. {/ j' n8.11 Stress Dependent ESD Behavior 263, u: ~' Y' }: |1 G
8.12 Failure Mode Case Studies 267. j% R; C0 \ \( D" h: w- F% o
8.13 Summary 271
, x8 B S2 h8 u. iBibliography 272
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