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Senior Physical Design Engineer
; N0 U' l0 I" A, ]: p公 司:A famous IC company
/ Y% @. \, m- j% Q; T6 }工作地点:南京
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3 F+ V; G8 a7 @8 r6 jKey Responsibilities " L Q v K3 J5 g+ Z% M8 m
Depending on experience, key responsibilities will involve some of the following:
2 a5 l$ E {; h4 M: bIC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification. + F6 p& O1 y8 A
As a key member of physical design team, your will work on one of most advanced and the most complex chip designed. ' R8 _6 b" p5 c
Leading a team of physical design engineers and resolving the technical related issues. ' O& |: C' S9 Z% _3 r1 m. s# u
Crosstalk analysis, power analysis, and static timing analysis. / J: \$ ?. \, O/ o! X
Write scripts in Tcl to improve productivity. : ]9 l1 ?* ?# ]. L- T
/ U: M' }% J, E: o$ s! KExperience: 5+ years in physical implementation engineering
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Essential skills
& ]! I% X& T8 Q! aMS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills $ y7 L8 m; c4 }. t5 z6 G( y0 l
Experience with Magma or Synopsys place-and-route tool set and physical design project implementation. + _* G% J9 Q3 d* n3 G3 M) R5 {2 U
Good programming skill. Capable of writing Tcl or Perl.
' O7 g) G0 K; p5 \Familiar with synthesis, static timing analysis.
, ^; u# C2 L1 k, X% g( H2 Q! \Self-motivated team worker, good verbal and written communication skills in English.
* g0 m7 ^: Q, D' l& O7 x! qTechnical and team leadership proffered. Previous management experience highly desired.
" F) G, e' `$ T( N7 g* w" BExperience with synthesis, DFT, and verification is preferred. |
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