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[問題求助] VHDL PS/2 Keyboard 程式問題..thx

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發表於 2008-1-23 17:29:22 | 顯示全部樓層 |閱讀模式
目前需要使用MAXII 1270 做PS/2 Keyboard控制,在網路上找到了用VHDL寫PS/2介面,經過測試後正常,但輸出是8個Pin輸出(並聯),但我希望輸出為1個Pin(串聯)輸出,請問我該如果修改程式呢?請大家幫幫忙,給個意見,或者提供任何資料參考...thx3 Y; A' m$ @1 z

4 c, P" \2 G5 \5 l6 }程式如下:
' b( J, _0 B5 q-- PS2_Ctrl.vhd+ J8 L+ g5 z9 t" W! v
-- ------------------------------------------------
9 m' T: t; M+ L8 D9 U& J3 @! B, L; L-- Simplified PS/2 Controller (kbd, mouse...)
# l' V1 Z  L" B7 R-- ------------------------------------------------
# f* j3 P* }+ _' Q" V' k-- Only the Receive function is implemented !/ E: p/ i9 a0 ~3 o, Y
-- (c) ALSE. http://www.alse-fr.com/ o* [! }% w) g: k% ?, Y: N% h4 [
library IEEE;/ z5 @) E/ k4 |6 T1 x
use IEEE.STD_LOGIC_1164.all;+ U0 ^) U, s, J$ ]; |: Z" L
use IEEE.Numeric_std.all;
# n; F, n2 `9 f+ j0 J* Q-- --------------------------------------" g  C) v/ a; \1 n) i
Entity PS2_Ctrl is
1 N" Y) M- W0 m-- --------------------------------------$ ~/ x% o. d* c1 w2 j
generic (FilterSize : positive := 8);
" J/ {- Y. q6 g1 ~& q& gport( Clk : in std_logic; -- System Clock
5 t$ p; b% q# M0 \0 \& [$ z: q2 s4 W. T1 cReset : in std_logic; -- System Reset' {8 p  x7 T2 \
PS2_Clk : in std_logic; -- Keyboard Clock Line/ B% n. Q# K8 q; |
PS2_Data : in std_logic; -- Keyboard Data Line
! [' ]5 C1 _5 ?3 BDoRead : in std_logic; -- From outside when reading the scan code; L3 G8 t& l# `% c; L8 w+ Q. s
Scan_Err : out std_logic; -- To outside : Parity or Overflow error( Y1 i9 H2 X4 d
Scan_DAV : out std_logic; -- To outside when a scan code has arrived7 G1 m5 `7 k9 n. j5 K+ F
Scan_Code : out std_logic_vector(7 downto 0) -- Eight bits Data Out5 g; [- T* b& P/ o/ s
);3 x; s& n7 R! @4 {
end PS2_Ctrl;
. J7 F" {1 }7 M2 }' _7 k& J-- --------------------------------------' A9 L& [3 e' u! E/ [0 P
Architecture ALSE_RTL of PS2_Ctrl is+ ~7 H: i1 \3 I2 w- E
-- --------------------------------------, H$ Y( N7 g) [2 n5 w6 e
-- (c) ALSE. http://www.alse-fr.com
/ n/ \% F, B# H7 U3 y! a; Q4 |1 e-- Author : Bert Cuzeau.% J8 ?& j" W* f; V6 ~
-- Fully synchronous solution, same Filter on PS2_Clk.
+ W. U, H  \+ Z0 v2 }% l% `-- Still as compact as "Plain_wrong"...
- ~$ L$ V( J& r* ?- P-- Possible improvement : add TIMEOUT on PS2_Clk while shifting
. f& _  {! u: a& U7 [, N-- Note: PS2_Data is resynchronized though this should not be+ a4 e/ M6 N/ ?5 C# j
-- necessary (qualified by Fall_Clk and does not change at that time).
. u, n  L; `, u  e# `' ^6 D) j6 z-- Note the tricks to correctly interpret 'H' as '1' in RTL simulation.% P6 p/ J0 u  w7 i' Z5 d1 n& R4 }
signal PS2_Datr : std_logic;" P" w- l' e% t0 _
subtype Filter_t is std_logic_vector(FilterSize-1 downto 0);
) ^( e; S7 w- F9 [, Q; isignal Filter : Filter_t;
2 \8 t. N  z& ^signal Fall_Clk : std_logic;: K! I0 [9 m5 z, [4 p
signal Bit_Cnt : unsigned (3 downto 0);
, x3 _& }/ \$ ^% D& s2 ~signal Parity : std_logic;: U4 {/ M5 E* \9 w" ?: D9 ]
signal Scan_DAVi : std_logic;
0 W' F$ o5 @) d) L, Dsignal S_Reg : std_logic_vector(8 downto 0);
9 \0 C1 d8 ~4 i- Hsignal PS2_Clk_f : std_logic;
2 X1 {. \( R/ O! Y# h: \Type State_t is (Idle, Shifting);
; Q- B% C* `, o2 osignal State : State_t;9 {" _! o* Q$ C) P# L
begin& j; y" {$ G0 d* z8 o: N# E; }
Scan_DAV <= Scan_DAVi;
5 c% K, Z, H/ L-- This filters digitally the raw clock signal coming from the keyboard :
* ^! T+ D3 _: Z# F7 r( \-- * Eight consecutive PS2_Clk=1 makes the filtered_clock go high
/ v* o3 E9 B' @+ J! _! m-- * Eight consecutive PS2_Clk=0 makes the filtered_clock go low
* t: o5 N3 Z2 S% f$ R8 W7 D-- Implies a (FilterSize+1) x Tsys_clock delay on Fall_Clk wrt Data
3 N6 X5 k# C$ o0 V1 |& F, r% Y  C-- Also in charge of the re-synchronization of PS2_Data; `% Q9 P6 i8 U! t! U% v
process (Clk,Reset)
' ~1 N$ N8 B; x" xbegin
, W/ }/ l5 c" p" v5 N+ Bif Reset='0' then
6 k* O; C" b# u8 P5 j' ~PS2_Datr <= '0';
$ T5 Q; E0 L. XPS2_Clk_f <= '0';6 i, Q+ e4 P* F/ D
Filter <= (others=>'0');
, N/ |0 q4 V; ~" [/ ]  C  AFall_Clk <= '0';5 ^1 [+ o. _* F, f1 a
elsif rising_edge (Clk) then
" t, g; ^1 ]! U7 c- oPS2_Datr <= PS2_Data and PS2_Data; -- also turns 'H' into '1'
2 n0 h2 ^0 l0 O/ a0 q- Q4 DFall_Clk <= '0';
. w- S3 t3 r9 l/ T) @Filter <= (PS2_Clk and PS2_CLK) & Filter(Filter'high downto 1);6 e9 _- a. q3 a6 u- K( I* h3 [) L
if Filter = Filter_t'(others=>'1') then# K1 A; d7 X  g5 _: x! O1 X5 ^
PS2_Clk_f <= '1';8 l2 G- z& ~  b5 S
elsif Filter = Filter_t'(others=>'0') then! F) ?/ ^$ B9 S
PS2_Clk_f <= '0';
$ @( I+ a6 ^/ O/ M8 }3 Uif PS2_Clk_f = '1' then/ H- s  y* L7 y: W* M! i
Fall_Clk <= '1';( M. ?+ M7 {. \; l) L$ ^8 x
end if;
- g  ?! T# C2 ~( `end if;
4 F6 p1 m- ]: c' C% Vend if;8 u2 a4 r1 l/ {! o) _9 J) O5 {
end process;% X$ K" {7 O  G0 K& ^7 r; Z, t% u! g
-- This simple State Machine reads in the Serial Data5 f+ E9 U7 L' `6 o* L* N1 G. h
-- coming from the PS/2 peripheral.
4 W* z4 Q, ?+ C, [process(Clk,Reset)
& {3 \$ Y/ p- s, Q% R: Y$ {: Wbegin
8 z. i2 t8 t, E/ a$ U$ G- H8 f+ jif Reset='0' then* D. H5 L! [0 O4 M5 G
State <= Idle;4 W. c' S* g: z* H0 ], V/ `; Z
Bit_Cnt <= (others => '0');
8 i9 E1 z% c* e4 U/ YS_Reg <= (others => '0');2 d' U) D% j, n" X
Scan_Code <= (others => '0');
/ {. a' q6 H+ }1 rParity <= '0';9 O9 E( a: G5 B7 X/ i2 N2 A. B
Scan_Davi <= '0';2 [, y% N% i4 \& Q- u% t3 H
Scan_Err <= '0';: ^2 n$ x# A- P; ]
elsif rising_edge (Clk) then
9 c, v) x' ^; A) k6 Cif DoRead='1' then, n4 u; r  j/ I( O
Scan_Davi <= '0'; -- note: this assgnmnt can be overriden
  z( c5 i" r2 ~: J$ X* tend if;
6 T2 v4 \# P: D) L0 T5 c# C( pcase State is
+ M3 X8 D3 m. _; t! e( Awhen Idle =>
/ Q' l- g; k% A  EParity <= '0';
2 I6 J% i5 }4 R' \! o  @1 ^1 DBit_Cnt <= (others => '0');
6 X' P- b8 U2 E5 c. e-- note that we dont need to clear the Shift Register! z8 F3 q# q  o' Q7 x
if Fall_Clk='1' and PS2_Datr='0' then -- Start bit
- T/ p: t' J; u" z, |) f' DScan_Err <= '0';$ W5 R" a% o+ X! `
State <= Shifting;( m  Y( ]' a) Q, r. j% u  M8 R
end if;
1 b' n- e0 ^7 t; L+ Vwhen Shifting =>+ c+ q0 m  f; b. `. F( @* E4 c( W
if Bit_Cnt >= 9 then
- G! p8 n' e+ h5 {5 Iif Fall_Clk='1' then -- Stop Bit0 N8 j3 R6 a5 W  o. {0 k
-- Error is (wrong Parity) or (Stop='0') or Overflow
! D, C, R1 M7 i' H5 MScan_Err <= (not Parity) or (not PS2_Datr) or Scan_DAVi;
& p* F/ p4 A. a" T5 d7 [Scan_Davi <= '1';6 X9 B/ W! e. c) n9 v  E9 W
Scan_Code <= S_Reg(7 downto 0);3 W% D( B5 J2 v6 Y
State <= Idle;
6 @- m9 B& E) A) S& x7 ?end if;
- o1 C0 r+ w0 Felsif Fall_Clk='1' then7 f. g3 H) ]0 F% |1 E# U( G6 b: G
Bit_Cnt <= Bit_Cnt + 1;
( H( C- x7 P6 G$ FS_Reg <= PS2_Datr & S_Reg (S_Reg'high downto 1); -- Shift right) ~( g( w8 ^8 s, J/ d2 S: n8 I6 O% x
Parity <= Parity xor PS2_Datr;) P! Y& ]6 E6 T$ I) s' v( A  J
end if;
  q: l2 m/ P2 ^8 \! d6 B+ h( {8 p7 hwhen others => -- never reached
) C! q' L: s: S. Y; d2 W2 c1 [State <= Idle;
& K0 f  r; M6 l$ P" }, Uend case;1 T5 q6 N% p6 b% s2 b+ A: H' }4 l
end if;
6 J/ c5 U& d# o( i) z3 dend process;
- v0 Q0 T: O- }1 D% ~. fend ALSE_RTL;
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