FPGA verification Engineer most difficult job functions?

ranica

Staff Verification Engineer

* Q8 i, A& W$ p3 {* h4 p0 o4 k公      司：one famous IC company
工作地点：上海
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Qualifications
MS in EE/CS/ME.  
Minimum of five  years experience.
Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
Candidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
Candidate should be familiar with industry standard ASIC design and verification tools and flow.
' j7 }! \* L9 S2 m* ?) vGood knowledge ddr protocol and computer system achitecture would be an added advantage.
* @% T% f+ c* P0 S0 _Good knowledge of Perl and shell programming would be an added advantage.  
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Responsibilities:
  ~0 }. H! L2 K. k, |) F- y+ ?) o-Understanding the expected functionality of designs.
2 b' P/ R* W/ C* k  q' a9 r+ V4 t$ }-Developing testing and regression plans.
! D8 ~. S, z& e' U  d) r$ R+ I8 K# O-Designing and developing verification environment.
4 A2 ], l$ B8 Y+ P( \+ T7 i) ~2 \-Running RTL and gate-level simulations/regression.
-Code/functional coverage development, analysis and closure.

! ~, Z7 a; n' \/ R& C+ n0 eRequirements:
. ^% u: D" X& s1 T8 _Experience & Skill: 5 Years
-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
-Knowledge in ASIC/FPGA design process and verification tools.
- w. h; T6 {. b-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
9 ~$ f2 q5 e: e! }7 |- Scripting and automation skills (tcl, perl, makefile etc) a plus.
1 {6 Y+ [9 N3 J1 c-Familiar with C/C++.
-Knowledge of DDR protocol a plus.
-Independent and self-managing.

ranica

Digital Design Engineer
& W7 y$ [$ h& {0 o9 m
公      司：A famous IC company
工作地点：上海
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Duties
Work with internal and external customers to understand product requirements.
5 j7 {. c9 L& ~. V. _1 tCreate critical silicon technologies to meet the product requirements.
+ ~2 n, }3 R# L9 B6 `4 Q' aWork out critical design flows and methodologies to execute implementation flawlessly.
4 l8 W. r* y" C  L" K+ }2 W. eDesign and deliver final design through multiple stages like specification, micro-architecture, IP  development, RTL coding, verification, logic synthesis, DFT, timing convergence, as well as helping on physical implementation.
Complete full documentation.
Help and mentor junior engineers.
8 P. o9 l2 H& t
Job Requirements:  
Solid understanding of all SoC chip development stages is required.  
Hands-on Experience with complex SoC design flow is required.  
, a" A& d+ w6 L6 V% X( c. LHands-on Experience with RTL coding, simulation, verification is required.
8 J; F! H* ?  H& \% oExperience with DFT and timing tools is preferred.
+ ~- Z, {! l: E8 EExperience with ARM platform is preferred.
Experience with low power design flow is preferred.
$ ~' D# s# L$ A9 v3 A# Q1 UExperience with system verilog is preferred.
Good organization and documentation abilities  
MS in Electrical Engineering and Computer Science with 4 years of experience in SoC design

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