FPGA verification Engineer most difficult job functions?

ranica

招聘公司：A fabless IC design company
招聘岗位：系统产品经理
工作地点：Beijing

' e. J$ t3 Q& }* d2 R岗位描述：
2 W7 j$ x& l9 i  d主要职责： 定制芯片的实际应用方案，为客户提供具体系统应用的解决方案，统计芯片在应用中出现的问题并形成改进建议书。

职位要求：
职位需求： 1. 计算机、通信、电子工程类专业，本科及以上学历。英语CET-4级以上水平，良好的英文读写能力； 2.了解民用消费类产品的框架结构及应用领域； 3. 具备较强的芯片级理解能力，对高速视频接口（LVDS, DVI, HDMI, DP）、数字电视相关芯片有深入的研究或应用，可以很准确的知道芯片的指标含 义和解释； 4. 熟练掌握 Cadence或PowerPCB/Powerlog ic等软件，熟知原理图设计，PCB 的布线规则和产品的生产流程。能够独立调试系统板级硬件； 5. 具备敏锐和快速的反应能力；良好的思维能力、信息收集、分析能力； 6. 良好的团队合作意识和沟通能力； 7. 适应经常出差，勤奋刻苦，爱岗敬业； 8. 具有较强的嵌入式软件编程能力，熟悉LINUX系统的应用。能够独立调试系统系统软件； 9. 具有产品应用及管理经历者优先。

ranica

招聘公司：A famous IC company
招聘岗位：SoC System Verification Engineer
工作地点：Xi'an
' k5 M" {# Y9 q9 c2 h2 o
岗位描述：
: M0 C% C( i' U3 y/ LJob Description: * Defines and develops system validation environment and test suites. * Hardware System Validation of Baseband ICs and peripheral for Mobile Terminals Technical coordination possible depending on experience and skills * Functional verification of the baseband IC and analyze of the occurring problems * Definition and implementation of test cases for the different modules(HW/SW, Low level drivers, Linux drivers) * Lead internal customer support during the evaluation phase * Interface to Concept Engineering Team, Design Team, SW Team

ranica

职位要求：
2 L/ D$ S4 ?2 ?% F5 fJob Description: * BS. or MS. Degree, MS. preferred, in Electrical / Electronics Engineering or equivalent * Minimum 2 years experience with the following tools/domains are recommended: * Knowledge of Embedded system * ARM Tools (ADS), GCC know how * Script languages (GNU Make, Make, Make File structures) * Debug Tooling Multi-ICE, Lauterbach, OS-aware debugging * RTOS Symbian, Nucleus, Linux or equivalent * Usage of C models (Virtual Prototype) to test Software before silicon availability * Configuration Management (Versioning Tools: ClearCase) * Knowledge of the following cores/architecture concepts are recommended: * ARM 7/9/11/Cortex Series and all controller functions: Interrupt/DMA... * Multimedia concept: JPEG, MPEG, Camera, Display, Multimedia Card Storage devices... * Standard Interfaces (UART, SSC, I2C, USB HS, USB FS, USB HSIC, MIPI HSl, SlimBus, MIPI Unipro¿) * Memory devices (DDR1, DDR2, SDRAM, Mobile RAM, NAND and NOR Flash) * Connectivity functions: WLAN, BlueTooth, GPS, FMR... * Good English, Excellent communication skill and team spirit oriented

ranica

招聘公司：A famous IC company
招聘岗位：Digital Design Engineer
+ E4 q: B. T/ ^) g7 y, ^" C工作地点：Beijing
' x# g  Q* l$ U+ I! P
: D4 W& X  B2 y& u& {9 H岗位描述：
Duties · Digital design, including synthesis, timing simulations, power optimization, DFT · Mixed signal design; and verification · Define, develop, and implement characterization, test plans, test vector generation · Work with other division test groups inside/outside FSC to identify possible co-operative opportunities to optimize test solution · Work on the design of analog blocks like voltage regulators, I/O buffer, output drivers, voltage references, oscillators · Work with product definition; characterization, and test engineers in the full product development flow; Work with application & test engineers to define optimal design and characterization solutions, based on design objectives · Layout floor planning, including P&R, DRC, LVS, and LPE
7 B6 G, h- k3 O& z. ]
职位要求：
3 j0 R% u  t3 t4 i- ^Requirements · Minimum 3 years direct digital IC design experience · Minimum 3-5 years direct mixed signal IC design experience · CMOS mixed signal circuit design and proficiency with industry standard design tools and Verilog/VHDL · Knowledge in CMOS/BiCMOS Analog circuit design Experience in Cadence IC Design tool set, simulation, verification · Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus Team-based, cross-functional organizational structure experience preferred · Excellent written and oral communication and presentation skills · Satisfactory written and oral communication skills in English · MSEE degree or above or equivalent experience · Strong communications skills; written, verbal, presentation and listening; · Good interpersonal skills to work in a team environment; · Good command of written and spoken English required; · Excellent interpersonal, written communication and presentation skills

ranica

招聘公司：A famous IC company
$ u6 u! f! y) I" G招聘岗位：Sr. Design Engineer
( a' e8 L  X9 N5 y工作地点：Shanghai、Beijing

$ f: q& G: _% X- e6 o) o2 g岗位描述：
Duties · Analog IC circuit design, simulation and verification · Design analog products and blocks such as high current or high capacitive load output drivers, operational amplifier, comparator, voltage reference, oscillator, error amplifier, voltage regulator etc. · Design of the switching power IC, DC-DC converters, for mobile/portal application · Evaluation, simulation and analysis of power architectures and circuit topologies · IC layout including floor planning, DRC, LVS, and LPE · Work with application and testing engineers to define optimal characterization and testing solution · Work with product definers and product engineers in full product development flow
, K" K  v7 g1 k/ ?
' s; F9 u8 `& C( K& _4 p3 W职位要求：
Requirements · Minimum 5 years direct DC-DC IC design experience, with MSEE or above degree · Strong knowledge in analog CMOS and Bipolar IC design · Working direct experience with switching power supplies, DC-DC converters, Battery charger, and their various topologies · Theoretical understanding of the power electronics, switching power supply topologies · Prior experience with power management related IC design a strong plus · Knowledge in analog IC layout · Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus · Excellent written and oral communication and presentation skills · Satisfactory written and oral communication skills in English · MSEE degree or above or equivalent experience · Strong communications skills; written, verbal, presentation and listening; · Good interpersonal skills to work in a team environment; · Good command of written and spoken English required; · Excellent interpersonal, written communication and presentation skills

ranica

招聘公司：a top 15 semiconductor company
- o. g! |% i" Z: B7 c1 p招聘岗位：Product Engineer
8 ]3 K, ^/ N2 O& B- {6 A6 U# h工作地点：Beijing

岗位描述：
" z" k. O9 a( b! q/ ]+ f- Design database verification by simulation and on FPGA - Chip function evaluation - Develop test firmware and tools (Hardware and Software) - Develop evaluation board - Cooperate to debug chip issues - Customer support • Assist with customers’ issues • Visit customers and provide on-site support • Build up demo system

# i' W1 I7 n- L6 A# O6 o0 g9 N& M职位要求：
- BSEE or above with minimum 3 years communication system experience - Familiar with Verilog. Has digital design experience with Verilog in real project - Minimum 3 years FPGA working experience, including code writing, timing analysis, debug - Familiar with at least one of schematic and PCB layout tools - Excellent English skill will be required. - Strong inter-personal, teamwork and communicational skills

ranica

客户 A famous IC company
地点 Shanghai

职位描述
We are looking for a person to join a design team to execute a state-of-the-art IC design project in the wireless communication field. Candidate must be familiar with digital IC design flow with a proven record of design and verification of a complex design project that led to successful silicon. Proficiency in Verilog is required.

7 d8 c3 ^+ S: x% m) ~4 T职位要求
$ u* K7 n, E8 x/ S9 h. cExperience in the following areas of expertise is desired:
8 L6 a8 w" A) G8 M  X  z- z$ _Wireless media access control (MAC) design experience would be highly desirable
6 I. D! w% Q$ sKnowledge of TCP/IP and DMA Offload Engine design experience will be a plus
. n/ X7 n6 ^3 a- v3 E- o1 ARTL design, verification, and chip integration
* J3 ?7 o* B5 K6 a) s+ @+ {  FExperience in the following is beneficial but not necessary requirement:
Communication systems and RF systems
7 q3 O& s- d& k5 L  T5 A6 EFamiliarity with wireless communication systems and standards (802.11b/g/n and WiGig)
Knowledge of interface protocols such as PCI/PCIe would be a plus
  g- a% `: K* k; ]FPGA design flow, testing, and emulation bringup
& W6 ^+ o- K: U3 U  t: h
- |* t2 ^7 Z; fOther requirements:
% j, Y0 h* x/ N+ A+ N. |Familiar with design and verification languages, EDA tools and ASIC/SOC design methodology
Good script language skill, such as Perl, Tcl and Shell
Good written and oral communication skills in English
7 N1 G, P/ s6 z* Y6 T6 J/ CGood Team player
" f) Z5 v7 g8 Y! y# _  s2 ?) [4 D1 wCandidates must have MSEE degree with at least 5 years of experience

ranica

招聘公司：A famous IC company
招聘岗位：高级ASIC设计工程师
工作地点：Shanghai
. U; X5 l# H6 j5 L2 \
1 _1 j% A* d7 B/ O岗位描述：
1、定义设计模块结构并编写芯片设计规范； 2、使用VHDL/Verilog编写逻辑模块的RTL代码； 3、编写测试向量对模块进行仿真验证； 4、在FPGA平台上进行芯片级的测试验证； 5、进行模块级的芯片综合与时序分析； 6、编写完整的设计和验证报告。
: j( u/ `# \& S3 {8 s
职位要求：
1、具有电子或通信工程类硕士以上学历； 2、 熟练运用Verilog/VHDL进行芯片前端设计，熟练运用设计仿真综合和测试工具，如quartus，Xilinx，modelsim，nc，debussy，逻辑分析仪，信道仿真设备等； 3、深刻理解数字电路设计和时序分析方法，并拥有故障定位和解决问题的能力； 4、深刻理解通信原理、数字信号处理等基础知识，熟悉无线通信原理与常用算法； 5、具有3年以上芯片设计经验，拥有无线通信物理层开发项目（如DTMB、CMMB、DVB、3G, LTE等）经验者优先； 6、工作认真严谨，积极上进； 7、良好的团队合作意识和沟通能力。

ranica

Verification Engineer
2 K1 r: [; m" P3 z7 @$ B- s
公      司：A famous IC company
1 d' g  V6 c2 Y. B+ r" @1 S工作地点：上海

7 |0 h, l% ^. i  q5 N$ d0 n) h! I" H0 i. FThe Role:
0 I- z/ G. e% N% T·         ASIC  verification
·         Work closely with the California teams
8 |% u8 \$ H) D·         Support chip tape out and bring up

2 R8 k$ o3 s3 Z& |4 f% T$ {Requirements:
·         3+ years experience in ASIC Verification
·         BS in Electrical Engineering (or equivalent) is a must have, MSEE is desired
·         System on Chip (SOC) Verification Experience, including AHB/AXI, CPU, Interface integration verification
/ r) W6 D* s' d% Y6 V) j·         Very familiar with verification languages – Verilog, System-Verilog, and VMM
·         Test plan and test case documentation
0 z. s  R( n7 T' J( W·         Functional coverage and code coverage analysis
·         Must be familiar with various scripting languages used in verification, including Perl, Csh, Make, etc.
3 Z3 k% g5 m8 g5 A  E8 t·         Experience verifying interfaces such as PCIe, Ethernet, DDR, USB
·         Working knowledge of networking protocols 802.3 and 802.11, especially Medium Access Control and TCP/IP
·         Working knowledge of C programming language
·         Must be familiar with the ASIC verification flow from feature identification to test bench development and through final tape out sign-off
* d/ y6 |! D0 Q* E) h4 s·         FPGA emulation experience a plus
·         Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging

ranica

ASIC Digital Verification Engineer
/ ^8 q7 b( a' ~5 b# A9 q公      司：A mobile chipset semiconductor company
工作地点：上海

5 N; r! G- @8 AResponsibilities:  
  Make verification plan for one module or whole chip.  
  Build up and maintain module-level and chip-level verification environment  
  Verify ASIC digital design based on case list, and output verification report.  
/ p( v& ]2 e0 B% a  Also responsible for lint checking and formal verification.  
; l- U5 _" Y) {9 Y* ]4 k, i- ^! s* Z
Qualifications:  
7 \, C! @' ]* v( L; n  Proficiency in logic verification.  
; U/ y0 ?! \3 x+ d& N- g% [  Experience with Verilog logic design language.  
% w) H1 Y* o! N; P  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.  
  Experience with UNIX/Linux simulation tools such as IUS or VCS.  
  Experience with C and C++ is a plus.  
  Experience with C_SHELL, TCL or PERL is a plus.  
! g9 ~3 d+ ^* e5 m" M/ I  Experience with UVM, OVM or VMM is a plus.  
) Y; T1 g% J/ E3 V' S7 o, J+ h  Good knowledge of SOC design is a plus.  
6 O. j( v  o* f0 `  Good knowledge of software design is a plus.  
  Self-motivated and good team player.  
  MSEE or BSEE with 2+ years.

tk02561

Hardware Applications Engineer–Graphics
公      司：A famous IC company
工作地点：上海
' _* z; s  l* c  Q* f4 \3 I
: @# G5 Q$ W3 q- aDesirable
Strong understanding of microprocessors
& ^/ f+ d* x& V, AA good understanding of the interaction between software and hardware
Understanding of FPGA or ASIC implementation flows (synthesis, scan insertion, layout)
' G! y* R  h  I6 b2 b* \C/C++, assembler coding or other programming skills.
  P- y) ]1 G- R0 bKnowledge of GPU or graphics processing specification, like OpenGLES, Direct-X, is preferred

1 F. W2 H7 q# g, }Job Requirements：

tk02561

Education
, J1 |/ b, P3 m2 K0 nGood university degree, in Computer Science or Electronics Engineering ideally, although other science graduates would be considered if they have relevant experience.
  
Experience
3 X% L0 Q3 t4 ^- R1 ~9 o* JMinimum of 4 years industrial experience
( N3 P3 e) i1 Y6 ^& \6 OExperience or knowledge of FPGA or ASIC design, simulation and/or verification techniques, including RTL coding and simulation, in Verilog or VHDL
; q# @4 E- [: E# p% wExperience in integrating SoC peripherals
- O: ?2 `7 u0 X+ e/ h  yExperience of interacting with colleagues outside of China
4 I5 W% ~0 F7 B8 D8 M  ^Professional experience of customer and sales interaction
Demonstrable experience of problem solving and debug skills
2 r5 \5 B1 J$ W) O9 ^# [
# [9 {! o7 o$ m  l- z0 aPersonal Requirements
Must have excellent written and verbal communication skills with both colleagues and customers, including good written and spoken English
& c. j3 J8 r7 c: LMust be proactive in obtaining engineering or management input, in order to complete project and internal tasks in a timely and accurate manner
Must have the desire and ability to solve problems quickly
Must be enthusiastic and well driven
Must be able to schedule own workload and plan tasks – based on both internal and customer requirements.  
$ l; e, l: [" X* OMust have good inter-personal skills, and be able to work well within a team; especially when under pressure
7 Z3 x' Y7 u  T4 I( BMust be willing to be flexible and accept new challenges
5 j) }! @6 n( F5 E6 ZMust be able to travel on a regular basis, both to give customer training and also for internal business reasons.

ranica

Senior Digital Design Engineer
  ?2 c# N' T3 c% r公      司：A leading semiconductor company
* Q- f* l6 r; S( u- e3 l' k! r工作地点：香港
' ]+ y' W, u2 A. P( n
9 k8 Y* `2 U; l9 E  d( NJob Responsibilities:
* n6 \& g! E4 t; L: D! ~2 s    Perform logic design, RTL coding, design verification, logic synthesis, DFT and static timing analysis
    Develop verification environment and coverage closure
  X3 f4 Y( z; K    Support wafer level testing and silicon evaluation
    Prepare technical documents
3 [" g! I/ ^4 f$ i
Job Requirements:
    B.Sc or above in Electronic Engineering or equivalent. Applicants with postgraduate degree would be considered as an advantage
    5 Years or above of solid experience in one or more of the following areas: Verilog-based logic design and synthesis, constrained random    testbench with System Verilog & UVM, assertion based design verification or circuit-level SPICE simulations
" ?/ B- _" p# o    Knowledge of SoC and embedded system.
    Knowledge of scripting languages such as Perl, TCL and Make
    Candidate with less experience will be considered as Digital Design Engineer

ranica

数字IC验证工程师
公      司：A famous IC company
9 }$ o" l) Q/ Z6 D, w$ g0 \, O3 J& p工作地点：上海

岗位职责：
1、负责整个团队验证平台的搭建、维护
2、先进验证方法和验证平台的评估、导入
3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。

职位要求：
1、大学本科及以上学历，电子、通信、计算机或微电子专业；
- V+ J; _1 r; F2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础；
3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等；
0 A3 |3 A. I# J% D0 p; H3、有1~2年芯片验证的相关工作经验；
4、具有较强的学习能力、沟通能力和良好的团队合作精神；
& p% T: [9 {# e; [! G+ ^! T4 |5、有基于ARM处理器的SOC芯片验证经验者优先考虑。

jcase

数字IC验证工程师
$ ?. |, L' [" @' F5 g公      司：A famous IC company
工作地点：上海
. A2 m6 M! |; h/ X  W, X
7 ^+ \4 V# L) L7 V2 b9 p岗位职责：
1、负责整个团队验证平台的搭建、维护
% S: F5 M! u0 T2、先进验证方法和验证平台的评估、导入
3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。
% j" I. _; n  f. o& h- C
1 a& B  w0 K, n6 \0 f, ]" V; t职位要求：
1、大学本科及以上学历，电子、通信、计算机或微电子专业；
- e7 P& ]0 l/ W2 S* k2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础；
$ e  i" ^0 x4 X0 L3 s/ [3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等；
. B3 k  M, d$ p" O: K$ r/ K! _3、有1~2年芯片验证的相关工作经验；
4、具有较强的学习能力、沟通能力和良好的团队合作精神；
5、有基于ARM处理器的SOC芯片验证经验者优先考虑。

ranica

Senior Digital Design Engineer
5 H/ H% R5 q; a1 p" A( N) W; p公      司：A famous European IC company
工作地点：上海
* ]" m- c( M0 y4 s# \, y7 }
Job description  
- define system partitioning of s/c circuits and system  
- define HW/SW co-partitioning  
- provide technical feasibilities based on system simulation and/or FPGA based demonstrator  
& U3 z! }' C, e: S- propose new technical solutions on s/c and system level  
- design digital part of mixed signal (smart power) ASICs  
- close cooperation and interaction with international teams  
- coach junior engineers  

: i3 k9 T+ I. l! m9 ~Required knowledge competencies and attributes  
) C" q/ _. E! ~8 d( E8 l- master degree in microelectronic circuits or systems, Communications, Computer Engineering (or equivalent)
& x, T7 J, R, _  ~7 ]( U- > 5ys experience in digital design  
- good understanding of ASIC mixed signal flow (Cadence based)  
- strong background in HDL coding, verification and toplevel integration  
+ {$ H* Q( A$ d3 E: _- good understanding of communication interfaces used in Automotive (SPI, CAN, LIN, Flexray)  
- experience in FPGA development  
- very good communication skills (written, oral)  
- self motivated and high level of flexibility  
- foreign languages: English, German (not a must)

sophiew

数字IC验证工程师
1 f' {( T( ~. ^, M) H公      司：A famous IC company
" I, O! O. P& q% ~) `工作地点：上海

& h! R6 e2 d) ?0 m岗位职责：
1、负责整个团队验证平台的搭建、维护
2、先进验证方法和验证平台的评估、导入
" R, l4 S5 M7 |* f1 T2 ?; _3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。

职位要求：
1、大学本科及以上学历，电子、通信、计算机或微电子专业；
2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础；
3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等；
3、有1~2年芯片验证的相关工作经验；
4、具有较强的学习能力、沟通能力和良好的团队合作精神；
- O1 A3 _7 ]: _3 `. Q5、有基于ARM处理器的SOC芯片验证经验者优先考虑。

ranica

ASIC Verification Engineer (WMAC)
: B/ z2 q/ X) F, j) F/ P5 D公      司：A famous IC company
工作地点：上海
+ P2 C0 T0 G# H; l
% ^3 B8 l1 y( j# H8 y: y' s8 M* BThe Role:
        ASIC design and verification
  [$ _) s+ B- k6 M/ L6 K        Work closely with the California teams
        Support chip tape out and bring up
5 a+ F+ E9 Z# D. z2 }! a: N6 q; u
3 E; ?$ ^: j9 P1 F3 fRequirement:
        8-10 yrs. experience  
- c) V4 o( `4 Y% u        Knowledge of Verilog / System Verilog & Perl
        Has worked on complex project; experience with 802.11 is preferable
        Can work independently - want him to take over MVE
        Experience in Networking SOC, Ethernet MAC or any other MAC layer protocol experience is plus

ranica

ASIC Digital Verification Engineer
公      司：A mobile chipset semiconductor company
9 z% r) q! l1 I# z) y工作地点：上海

Responsibilities:  
  Make verification plan for one module or whole chip.  
  Build up and maintain module-level and chip-level verification environment  
% D3 n* i. g: M  Verify ASIC digital design based on case list, and output verification report.  
  Also responsible for lint checking and formal verification.  

3 U; n, x) a2 HQualifications:  
0 f, U" O' Z% H  Proficiency in logic verification.  
  Experience with Verilog logic design language.  
: M8 e. O9 e# v: Z5 P; R: w* }: g  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.  
  Experience with UNIX/Linux simulation tools such as IUS or VCS.  
6 F: q  z: [( E% w  Experience with C and C++ is a plus.  
  Experience with C_SHELL, TCL or PERL is a plus.  
  Experience with UVM, OVM or VMM is a plus.  
' @. j4 y: [( ~2 h  Good knowledge of SOC design is a plus.  
6 \- `; e; Q2 x# r  Good knowledge of software design is a plus.  
  Self-motivated and good team player.  
  MSEE or BSEE with 2+ years.

ranica

Staff Verification Engineer
公      司：one famous IC company
工作地点：上海

' a$ d0 N* |5 CQualifications
MS in EE/CS/ME.  
  }& o6 p  ~( {& ~1 x2 T1 _: RMinimum of five  years experience.
Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
" G/ _2 n, a4 ]8 g3 A7 nCandidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
% h& M2 l! \/ t: H0 lCandidate should be familiar with industry standard ASIC design and verification tools and flow.
+ W* K) {7 _2 Z/ i. KGood knowledge ddr protocol and computer system achitecture would be an added advantage.
* a- X, f; ?6 X3 }2 a5 }0 P, zGood knowledge of Perl and shell programming would be an added advantage.  

# n8 `: I$ G4 a# o1 u1 XResponsibilities:
-Understanding the expected functionality of designs.
-Developing testing and regression plans.
/ Q# E1 M5 o0 b5 y% r" _-Designing and developing verification environment.
2 e7 [6 Q, r. J, f* M5 }( z* X-Running RTL and gate-level simulations/regression.
4 z, ?/ j4 I0 `) h7 m+ m7 L2 ~-Code/functional coverage development, analysis and closure.
2 S% s0 z/ J0 b6 o! A) |; o
Requirements:
$ g" N# ~# z/ p2 B! q4 r: d3 rExperience & Skill: 5 Years
- H" A7 T$ q) S1 a) l; U-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
-Knowledge in ASIC/FPGA design process and verification tools.
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
- Scripting and automation skills (tcl, perl, makefile etc) a plus.
- g# m" g' j  D3 V1 n8 ~-Familiar with C/C++.
" {1 K( K- s. D  \) c-Knowledge of DDR protocol a plus.
-Independent and self-managing.