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請教 Synplify Pro9.6.1 Warning Message
- R: g H- L* LSequential instance sLateCol_p has been Sequential instance sLateCol_p has been reduced to a combinational gate by constant propagation& [/ L2 C! E( S
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請教個問題,下面是Synplify 9.6.1 出現的Warning message ,5 w# B) P% Q& I, D
請問這是什麼意思 ??/ B- D4 t) B, K5 J( `: U
我由字面上的理解得到的猜測是,將一個本應該是FIFO Sequential circuit ,合成為 Multiplier Combinational circuit2 T3 v2 W$ F( @0 q1 e
為什麼 ld_tdr_cur_f 會被合成為Combinational, 但是 dly_tdr_wrn 卻不會 ??$ G5 p l& e9 r9 X5 g% \ r
誰有相關的經驗嗎 ??/ Z9 {/ D% E+ h" A$ |
) Z& q/ o; J6 D M. ^4 q- B. Y@W: MO129 :"\projects\dm8606c\rtl\tff256x64.v":932:3:932:8|
9 [* j: G0 |. B& o: K( jSequential instance ld_tdr_cur_f has been reduced to a combinational gate by constant propagation/ J6 f: m- T- n& Q, A% |& z5 S
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reg ld_tdr_cur_f;
( r* o) t( ~ Y" n( M! W& y% X; O reg dly_tdr_wrn;1 n" K1 k. H. [6 W Y# q
//------------------------- g1 I. j+ Z* m. x! V2 x
// delay 1 clk F L. X5 r [ b
//------------------------
. r6 j1 z+ R" p* Y! U$ X! C; } always@(posedge sclk) " Z$ \0 u J1 _6 U
begin: _! M) P, D$ H7 a* O+ ~
ld_tdr_cur_f <=#td1 ld_tdr_cur;& r3 }: B1 O+ X: U5 L0 D& V
dly_tdr_wrn <=#td1 tdr_wrn;8 o8 D4 O2 r+ H0 G" w; m
end
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// 下面是 ld_tdr_cur_f , dly_tdr_wrn 的loading ; x8 T$ S7 K( t
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always @(posedge sclk)
6 Z0 ?5 v$ s3 A5 w" a if (ld_madr & !wr_nxt_tdr) 1 e8 P4 F" {* B, t: g3 h
wr_save_1st <= #td1 wr_counter;6 O& M) ?. o& P# L! j$ A
else if (ld_tdr_cur_f)
) ^4 J/ x. [# V9 Y wr_save_1st <= #td1 wr_save_2nd; 7 ` \# d* B9 `3 j/ _8 H
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always @(posedge sclk or negedge rstn)
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; \# C. G" ]6 ]6 Y( } rst_ff_pt <= #td1 1'b0;% q" O( }# v" e; [! P+ B; @/ k2 w
else ) @9 v7 U' L$ k8 F! Q6 I- s+ J
rst_ff_pt <= #td1 (!tdr_wrn & dly_tdr_wrn & tdr_empty);
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always @(posedge sclk or negedge rstn)! F# W6 C- Y/ K5 R# W
if (!rstn) ; M. x6 o6 N3 x. X% t/ H3 u
rst_ffpt_sync <= #td1 1'b0;0 J C$ A! V7 D3 e% x, K$ j
else if (!tdr_wrn & dly_tdr_wrn & tdr_empty) # ?9 ^0 R' |5 `7 C
rst_ffpt_sync <= #td1 1'b1;
& y8 w9 @0 c1 c' u5 r/ d/ r else if (rst_ffpt_clr2) , U# c5 V4 N% O7 \0 \
rst_ffpt_sync <= #td1 1'b0; |
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