Circuit and Layout Co-Design for ESD Protection in BCD

semico_ljj

Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process
& o$ z6 l' `2 K/ d
- B7 o4 R; G1 Z  K8 xWen-Yi Chen, Student Member, IEEE, and Ming-Dou Ker, Fellow, IEEE

Abstract—The n-channel lateral double-diffused metal–oxide–
- a: A; I3 d! s4 Y8 Isemiconductor (nLDMOS) devices in high-voltage (HV) technologies
are known to have poor electrostatic discharge (ESD)
robustness. To improve the ESD robustness of nLDMOS, a co-design
" @/ w. E) e7 J; J5 y1 s  |9 |method combining a new waffle layout structure and a trigger
circuit is proposed to fulfill the body current injection technique
# a8 V9 G, ~6 t* b8 W1 yin this work. The proposed layout and circuit co-design method
6 E* a# a: a, A* o% d$ kon HV nLDMOS has successfully been verified in a 0.5- m 16-V
5 j2 h. T( R1 bbipolar-CMOS-DMOS (BCD) process and a 0.35- m 24-V BCD
process without using additional process modification. Experimental
$ U& z: b: ?' S- _, J5 Mresults through transmission line pulse measurement
and failure analyses have shown that the proposed body current
injection technique can significantly improve the ESD robustness
* Q5 J" q5 f6 a7 N" A7 yof HV nLDMOS.

8 F; t  n! m6 Q$ }- xIndex Terms—Bipolar-CMOS-DMOS (BCD) process, body
7 l  ?& X, z0 A; t* J2 j+ c* ncurrent injection, electrostatic discharge (ESD), lateral double-diffused
6 G% N2 T. O7 Z% ~1 b, Xmetal–oxide–semiconductor (LDMOS).

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