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Optimization Layout of ESD:Radio-Frequency Front-End and High-Speed I/O Interfac

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發表於 2010-6-25 08:55:14 | 顯示全部樓層 |閱讀模式
Optimization on Layout Style of ESD Protection! H% F+ [& J, A* }# M* I
Diode for Radio-Frequency Front-End and High-Speed I/O Interface Circuits
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! k. i+ u) f# u5 wAbstract—The diode operated in forward-biased condition has been widely used as an effective on-chip electrostatic discharge (ESD) protection device at radio-frequency (RF) front-end and high-speed input/output (I/O) pads due to the small parasitic loading effect and high ESD robustness in CMOS integrated circuits (ICs). This work presents new ESD protection diodes drawn in the octagon, waffle-hollow, and octagon-hollow layout styles to improve the efficiency of ESD current distribution and to reduce the parasitic capacitance. The measured results confirmed that they can achieve smaller parasitic capacitance under the same ESD robustness level as compared to the stripe and waffle diodes, especially for the diodes drawn in the hollow layout style. Therefore, the signal degradation of RF and high-speed transmission can be reduced because of smaller parasitic capacitance from the new proposed diodes.
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% ^" j2 D/ b8 N' W( u9 ?Index Terms—Diode, electrostatic discharge (ESD), layout, radio-frequency (RF).
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發表於 2010-6-27 22:13:31 | 顯示全部樓層
pls share ,3q. because i am a emc
發表於 2011-5-13 16:48:47 | 顯示全部樓層
讚啦!! 正需要這篇
; _5 |* o7 y1 x. Dplease
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